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pocketinstrument [2020/08/21 17:23] gongyu [4 参考代码] |
pocketinstrument [2020/08/22 21:26] (当前版本) gongyu [4 参考代码] |
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### 3 核心器件技术资料及数据手册 | ### 3 核心器件技术资料及数据手册 | ||
- | * MAX1193-双路45Msps、8位高速ADC | + | * MAX1193-双路45Msps、8位高速[[ADC]] |
* SGM8301轨到轨高速运算放大器 | * SGM8301轨到轨高速运算放大器 | ||
* SGM8601高速运算放大器 | * SGM8601高速运算放大器 | ||
行 34: | 行 34: | ||
* LM2776电荷泵变换器 | * LM2776电荷泵变换器 | ||
* MIC5504-3.3 [[LDO]] | * MIC5504-3.3 [[LDO]] | ||
- | * 240*240 LCD模块 | + | * 1.54寸、分辨率为240*240的RGB[[LCD]]模块 |
### 4 参考代码 | ### 4 参考代码 | ||
- | * DDS任意波形发生器 | + | * [[dds_verilog|DDS任意波形发生器/可调直流电压发生器]] |
- | * 可调直流电压发生器 | + | * [[scope_verilog|与示波器相关的FPGA Verilog逻辑设计]] |
* [[ADCSampling|ADC采样]] | * [[ADCSampling|ADC采样]] | ||
+ | * [[LCD240*240Disp|240*240分辨率RGB LCD的控制]] | ||
+ | |||
+ | 数据ADC读出、LCD写入的状态控制 | ||
+ | |||
+ | <code verilog> | ||
+ | // -------------------------------------------------------------------- | ||
+ | // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< | ||
+ | // -------------------------------------------------------------------- | ||
+ | // Module: Arbiter | ||
+ | // | ||
+ | // Author: Step | ||
+ | // | ||
+ | // Description: Control sample and display in different time | ||
+ | // | ||
+ | // Web: www.stepfpga.com | ||
+ | // | ||
+ | // -------------------------------------------------------------------- | ||
+ | // Code Revision History : | ||
+ | // -------------------------------------------------------------------- | ||
+ | // Version: |Mod. Date: |Changes Made: | ||
+ | // V1.1 |2016/10/30 |Initial ver | ||
+ | // -------------------------------------------------------------------- | ||
+ | module Arbiter ( | ||
+ | input clk_in, // system clock | ||
+ | input rst_n_in, //system reset, active low | ||
+ | |||
+ | input sample_done, | ||
+ | input display_done, | ||
+ | |||
+ | output reg sample_en, | ||
+ | output reg display_en | ||
+ | ); | ||
+ | |||
+ | localparam IDLE = 2'd0; | ||
+ | localparam SAMPLE = 2'd1; | ||
+ | localparam DISPLAY = 2'd2; | ||
+ | |||
+ | reg [1:0] state; | ||
+ | always@(posedge clk_in or negedge rst_n_in) begin | ||
+ | if(!rst_n_in) begin | ||
+ | state <= IDLE; | ||
+ | sample_en <= 1'b0; | ||
+ | display_en <= 1'b0; | ||
+ | end else begin | ||
+ | case(state) | ||
+ | IDLE:begin | ||
+ | sample_en <= 1'b0; | ||
+ | display_en <= 1'b0; | ||
+ | state <= SAMPLE; | ||
+ | end | ||
+ | SAMPLE:begin | ||
+ | if(sample_done) begin | ||
+ | sample_en <= 1'b0; | ||
+ | display_en <= 1'b1; | ||
+ | state <= DISPLAY; | ||
+ | end else begin | ||
+ | sample_en <= 1'b1; | ||
+ | display_en <= 1'b0; | ||
+ | end | ||
+ | end | ||
+ | DISPLAY:begin | ||
+ | if(display_done) begin | ||
+ | sample_en <= 1'b1; | ||
+ | display_en <= 1'b0; | ||
+ | state <= SAMPLE; | ||
+ | end else begin | ||
+ | sample_en <= 1'b0; | ||
+ | display_en <= 1'b1; | ||
+ | end | ||
+ | end | ||
+ | default:state <= IDLE; | ||
+ | endcase | ||
+ | end | ||
+ | end | ||
+ | |||
+ | endmodule | ||
+ | |||
+ | </code> |