module dds_main(clk_in,led,dac_data,pwm_out);
input clk_in; //12MHz
output led;
output [9:0] dac_data;
output pwm_out;
reg [23:0] cnt; //???????
always@(posedge clk_in) cnt <= cnt +1'b1;
assign led= cnt[22]; //12MHz/2^21 ~ 6Hz
wire clk_96m;
CLK_96M u5(.CLKI(clk_in), .CLKOP(clk_96m));
//square wave generated by toggling all data bits from 0-->1--0
//wire cnt_tap = cnt[2]; // we take one bit out of the counter (here bit 7 = the 8th bit)
//assign dac_data = {10{cnt_tap}}; // and we duplicate it 10 times to create the 10-bits DAC value
//assign dac_data = cnt[9:0]; //Sawtooth waveform, frenquency = Fclk/2^10
// Triangle waveform, frequency = Fclk/2^11
//assign dac_data = cnt[10] ? ~cnt[9:0] : cnt[9:0]; // Triangle waveform, frenquency = Fclk/2^11
wire [23:0] next_phase;
wire [7:0] phase;
reg [23:0] accumulator;
assign next_phase = 24'H0DA7 + accumulator;
always @(posedge clk_96m)
accumulator <= #1 next_phase;
assign phase = accumulator[23:16]; // phase is the high 8 bits
wire [9:0] sine_data;
//lookup_tables u_lookup_tables(clk_96m, phase, sine_data);
LUT_sine_table U_lut_sine_table(.Clock(~clk_96m), .ClkEn(1'b1), .Reset(1'b0), .Theta(phase), .Sine(sine_data));
assign dac_data = sine_data[9:0] + 10'h1ff ;
wire [9:0] PWM_in;
//assign PWM_in = 8'd38;
assign PWM_in = dac_data[9:0];
reg [10:0] PWM_DDS_accumulator;
always @(posedge clk_96m) PWM_DDS_accumulator <= PWM_DDS_accumulator[9:0] + PWM_in;
assign pwm_out = PWM_DDS_accumulator[10];
endmodule