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stepfpgaboard [2019/04/24 08:37] gongyu |
stepfpgaboard [2019/04/24 08:55] gongyu |
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| - | ### 器件 | + | ### 器件总览 (还在编辑中) |
| + | {{ :fpgablock.png?800 |}} | ||
| ^器件系列|类型 | 厂商 | 逻辑资源 | 内部块存储 | 时钟 | 内部硬核 | 乘法器 | I/O |编译系统 | | ^器件系列|类型 | 厂商 | 逻辑资源 | 内部块存储 | 时钟 | 内部硬核 | 乘法器 | I/O |编译系统 | | ||
| - | ^ICE | PLD/FPGA|[Lattice](http://www.latticesemi.com) | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| | + | ^ICE | [[PLD]]|[Lattice Semi](http://www.latticesemi.com) | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| |
| - | ^XO | PLD/FPGA|[Lattice](http://www.latticesemi.com) | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| | + | ^XO | PLD/[[FPGA]]|[Lattice Semi](http://www.latticesemi.com) | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| |
| - | ^ECP | PLD/FPGA|[Lattice](http://www.latticesemi.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| | + | ^ECP | [[FPGA]]|[Lattice Semi](http://www.latticesemi.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| |
| - | ^MAX II | PLD|[Lattice](http://www.latticesemi.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^ |
| - | ^MAX V | PLD|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^MAX II |[[PLD]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^MAX 10 | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^MAX V | [[PLD]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Cyclone V | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^MAX 10 |[[PLD]]/[[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Cyclone 10 | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Cyclone V | [[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Arria V | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Cyclone 10 |[[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Arria 10 | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Arria V | [[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Stratix V | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Arria 10 |[[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Stratix 10 | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Stratix V | [[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Agilex | PLD/FPGA|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Stratix 10 | [[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Agilex | PLD/FPGA|Altera/Intel | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Agilex | [[FPGA]]|[Altera/Intel](https://www.intel.com/content/www/us/en/products/programmable.html)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| |
| - | ^Agilex | PLD/FPGA|Altera/Intel | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^ |
| - | ^Agilex | PLD/FPGA|Altera/Intel | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Quartus II| | + | ^Spartan 6 |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| |
| - | ^Agilex | PLD/FPGA|Altera/Intel | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| | + | ^Spartan 7 |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| |
| - | ^Agilex | PLD/FPGA|Altera/Intel | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| | + | ^Artix 7 |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| |
| - | ^Agilex | PLD/FPGA|Lattice | 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Diamond| | + | ^Kintex 7 |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| |
| + | ^Virtex 7 |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||
| + | ^Kintex Ultrascale |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||
| + | ^Virtex Ultrascale |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||
| + | ^Kintex Ultrascale + |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||
| + | ^Virtex Ultrascale + |[[FPGA]]|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||
| + | ^ZYNQ 7000 |[[FPGA]]/SoC|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||
| + | ^ZYNQ Ultrascale + |[[FPGA]]/MPSOC|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||
| + | ^ZYNQ Ultrascale + |[[FPGA]]/RFSOC|[Xilinx Inc](https://www.xilinx.com)| 96Kb | 92Kb | PLL（2）|SPI、I2C、Timer | |DDR3|Vivado| | ||