// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Module: Pulse_gen
// 
// Author: Step
// 
// Description: Pulse generate module
// 
// Web: www.ecbcamp.com
//
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date:   |Changes Made:
// V1.0     |2015/11/11   |Initial ver
// --------------------------------------------------------------------
module Pulse_gen
(
input			clk_in,
input			rst_n_in,
input			key_menu,
input			key_up,
input			key_down,
output			menu_state,
output	reg		pulse_out
);
 
//Debounce for key_menu
Debounce Debounce_menu(.clk(clk_in),.rst_n(rst_n_in),.key_n(key_menu),.key_state(menu_state)); 
 
//Debounce for key_up
Debounce Debounce_up(.clk(clk_in),.rst_n(rst_n_in),.key_n(key_up),.key_pulse(up_pulse)); 
 
//Debounce for key_down
Debounce Debounce_down(.clk(clk_in),.rst_n(rst_n_in),.key_n(key_down),.key_pulse(down_pulse)); 
 
reg	[3:0] cycle;
reg	[3:0] duty;
//Control cycle and duty cycle
always @(posedge clk_in or negedge rst_n_in) begin 
	if(!rst_n_in) begin 
		cycle<=4'd8;
		duty<=4'd4;
	end else begin
		if(menu_state) begin
			if(up_pulse && (cycle<4'd15)) cycle <= cycle + 4'd1;
			else if(down_pulse && (cycle>(duty+4'd1))) cycle <= cycle - 4'd1;
			else cycle <= cycle;
		end else begin
			if(up_pulse && (cycle>(duty+4'd1))) duty <= duty + 4'd1;
			else if(down_pulse && (duty>4'd0)) duty <= duty - 4'd1;
			else duty <= duty;
		end
	end 
end 
 
reg	[3:0]	cnt;
//counter for cycle
always @(posedge clk_in or negedge rst_n_in) begin 
	if(!rst_n_in) begin 
		cnt<=4'd0;
	end else begin
		if(cnt>=cycle) cnt<=4'd0;
		else cnt <= cnt + 4'd1;
	end 
end 
 
//pulse generate with duty
always @(posedge clk_in or negedge rst_n_in) begin 
	if(!rst_n_in) begin 
		pulse_out<=1'b1;
	end else begin
		if(cnt<=duty) pulse_out<=1'b1;
		else pulse_out<=1'b0;
	end 
end 
 
endmodule