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--- pulse_gen.v [2016/06/14 14:37]
anran 创建
+++ pulse_gen.v [2016/06/29 13:39] (当前版本)
anran
@@ 行 5: / 行 5: @@
 // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
 // --------------------------------------------------------------------
-// Module: Debounce
+// Module: Pulse_gen
 //
 // Author: Step
 //
-// Description: Debounce for button with FPGA/CPLD
+// Description: Pulse generate module
 //
 // Web: www.ecbcamp.com
@@ 行 19: / 行 19: @@
 // V1.0     |2015/11/11   |Initial ver
 // --------------------------------------------------------------------
-module Debounce(clk,rst_n,key_n,key_pulse,key_state);
+module Pulse_gen
+(
+input					clk_in,
+input					rst_n_in,
+input					key_menu,
+input					key_up,
+input					key_down,
+output					menu_state,
+output	reg				pulse_out
+);
-input   		clk;			//system clock
+//Debounce for key
-input   		rst_n;			//system reset
+wire [2:0] key_state,key_pulse;
-input   		key_n;			//button input
+Debounce1 Debounce_uut
-output  		key_pulse;		//Debounce pulse output
+(
-output	reg		key_state;		//Debounce state output
+.clk(clk_in),
+.rst_n(rst_n_in),
+.key_n({key_menu,key_up,key_down}),
+.key_state(key_state),
+.key_pulse(key_pulse)
+);
-reg  key_rst;
+wire menu_state = key_state[2];
-//Register key_rst, lock key_n to next clk
+wire up_pulse = key_pulse[1];
-always @(posedge clk  or  negedge rst_n)
+wire down_pulse = key_pulse[0];
-    if (!rst_n) key_rst <= 1'b1;
-    else  key_rst <=key_n;
-//Detect the edge of key_n
-wire  key_an = (key_rst==key_n)? 0:1;
-reg[18:0]  cnt;
+reg	[3:0] cycle;
-//Count the number of clk when a edge of key_n is occured
+reg	[3:0] duty;
-always @ (posedge clk  or negedge rst_n)
+//Control cycle and duty cycle
-    if (!rst_n) cnt <= 19'd0;
+always @(posedge clk_in or negedge rst_n_in) begin
-    else if(key_an) cnt <=19'd0;
+	if(!rst_n_in) begin
-    else cnt <= cnt + 1'b1;
+		cycle<=4'd8;
+		duty<=4'd4;
+	end else begin
+		if(menu_state) begin
+			if(up_pulse && (cycle<4'd15)) cycle <= cycle + 4'd1;
+			else if(down_pulse && (cycle>(duty+4'd1))) cycle <= cycle - 4'd1;
+			else cycle <= cycle;
+		end else begin
+			if(up_pulse && (cycle>(duty+4'd1))) duty <= duty + 4'd1;
+			else if(down_pulse && (duty>4'd0)) duty <= duty - 4'd1;
+			else duty <= duty;
+		end
+	end
+end
-reg  low_sw;
+reg	[3:0]	cnt;
-//Lock the status to register low_sw when cnt count to 19'd500000
+//counter for cycle
-always @(posedge clk  or  negedge rst_n)
+always @(posedge clk_in or negedge rst_n_in) begin
-    if (!rst_n)  low_sw <= 1'b1;
+	if(!rst_n_in) begin
-	else if (cnt == 19'd500000)
+		cnt<=4'd0;
-        low_sw <= key_n;
+	end else begin
+		if(cnt>=cycle) cnt<=4'd0;
+		else cnt <= cnt + 4'd1;
+	end
+end
-reg   low_sw_r;
+//pulse generate with duty
-//Register low_sw_r, lock low_sw to next clk
+always @(posedge clk_in or negedge rst_n_in) begin
-always @ ( posedge clk  or  negedge rst_n )
+	if(!rst_n_in) begin
-    if (!rst_n) low_sw_r <= 1'b1;
+		pulse_out<=1'b1;
-    else  low_sw_r <= low_sw;
+	end else begin
+		if(cnt<=duty) pulse_out<=1'b1;
-wire  key_pulse;
+		else pulse_out<=1'b0;
-//Detect the negedge of low_sw, generate pulse
+	end
-assign key_pulse= low_sw_r & ( ~low_sw);
+end
-//Detect the negedge of low_sw, generate state
-always @(posedge clk or negedge rst_n)
-	if (!rst_n) key_state <= 1'b1;
-    else if(key_pulse) key_state <= ~key_state;
-	else key_state <= key_state;
-endmodule
+endmodule
 </code>