差别

这里会显示出您选择的修订版和当前版本之间的差别。

--- processor_opencore [2020/08/11 11:56]
xiesen 创建
+++ processor_opencore [2020/08/11 14:26] (当前版本)
xiesen
@@ 行 5: / 行 5: @@
 ####项目
 [[https://opencores.org/projects/c16|16 Bit Microcontroller]]\\
+[[https://opencores.org/projects/blue|16-bit CPU based loosely on Caxton Foster's Blue architecture]]\\
+[[https://opencores.org/projects/ourisc|16-bit Open uRISC core Processor]]\\
+[[https://opencores.org/projects/1664|1664 microprocessor]]\\
+[[https://opencores.org/projects/simplerisc_32bit_pipelined_processor|32 bit Processor]]\\
+[[https://opencores.org/projects/mcs-4|4004 CPU and MCS-4 family chips]]\\
+[[https://opencores.org/projects/6502vhdl|6502VHDL]]\\
+[[https://opencores.org/projects/6809_6309_compatible_core|6809 and 6309 Compatible core]]\\
+[[https://opencores.org/projects/68hc05|68hc05]]\\
+[[https://opencores.org/projects/68hc08|68hc08]]\\
+[[https://opencores.org/projects/mcu8|8-bit microcontroller with extended peripheral set]]\\
+[[https://opencores.org/projects/instruction_list_pipelined_processor_with_peripherals|8-bit Piepelined Processor]]\\
+[[https://opencores.org/projects/sap|8-bit uP]]\\
+[[https://opencores.org/projects/8051|8051 core]]\\
+[[https://opencores.org/projects/cpu8080|8080 Compatible CPU]]\\
+[[https://opencores.org/projects/my8085light|A lightweight 8085 verilog implementation]]\\
+[[https://opencores.org/projects/a-z80|A-Z80 CPU]]\\
+[[https://opencores.org/projects/ae18|ae18]]\\
+[[https://opencores.org/projects/aemb|aeMB]]\\
+[[https://opencores.org/projects/ag_6502|ag_6502 soft core with phase-level accuracy]]\\
+[[https://opencores.org/projects/altor32|AltOr32 - Alternative Lightweight OpenRisc CPU]]\\
+[[https://opencores.org/projects/alt_isa|alt_ISA]]\\
+[[https://opencores.org/projects/alwcpu|Alwcpu - A light weight CPU]]\\
+\\
+[[https://opencores.org/projects/amber|Amber ARM-compatible core]]\\
+[[https://opencores.org/projects/up_core_list|An inventory of soft processor cores]]\\
+[[https://opencores.org/projects/ao486|ao486]]\\
+[[https://opencores.org/projects/ao68000|ao68000 - Wishbone 68000 core]]\\
+[[https://opencores.org/projects/aor3000|aoR3000]]\\
+[[https://opencores.org/projects/agcnorm|Apollo Guidance Computer NOR eMulator]]\\
+[[https://opencores.org/projects/aquarius|Aquarius]]\\
+[[https://opencores.org/projects/arm4u|ARM4U]]\\
+[[https://opencores.org/projects/aspida|ASPIDA sync/async DLX Core]]\\
+[[https://opencores.org/projects/atlas_core|Atlas Processor Core]]\\
+[[https://opencores.org/projects/attiny_atmega_xmega_core|Attiny Atmega Xmega core]]\\
+[[https://opencores.org/projects/avr_core|AVR Core]]\\
+[[https://opencores.org/projects/avr_hp|AVR HP, Hyper Pipelined AVR Core]]\\
+[[https://opencores.org/projects/avrtinyx61core|AVRtinyX61core]]\\
+[[https://opencores.org/projects/ax8|AX8 mcu]]\\
+[[https://opencores.org/projects/biriscv|BiRiscV - 32-bit dual issue RISC-V CPU]]\\
+[[https://opencores.org/projects/brainfuckcpu|Brainfuck CPU]]\\
+[[https://opencores.org/projects/cf_ssp|CF State Space Processor]]\\
+[[https://opencores.org/projects/lwrisc|ClaiRISC - runs 12bit opcode PIC family.]]\\
+[[https://opencores.org/projects/mips32|Classic 5-Stage Pipeline MIPS]]\\
+[[https://opencores.org/projects/c0or1k|Codezero OpenRISC Port]]\\
+[[https://opencores.org/projects/or1k-cf|Confluence OpenRisc 1000]]\\
+[[https://opencores.org/projects/copyblaze|copyBlaze]]\\
+[[https://opencores.org/projects/cowgirl|Cowgirl]]\\
+[[https://opencores.org/projects/cpugen|Cpu Generator]]\\
+[[https://opencores.org/projects/cpu6502_true_cycle|cpu6502_tc - R6502 Processor Soft Core with accurate timing]]\\
+[[https://opencores.org/projects/cpu65c02_true_cycle|cpu65c02_tc - R65C02 Processor Soft Core with accurate timing]]\\
+[[https://opencores.org/projects/dfp|Data Flow Processor]]\\
+[[https://opencores.org/projects/diogenes|Diogenes: Student RISC System]]\\
+[[https://opencores.org/projects/distributed_intelligence|Distributed limited cores]]\\
+[[https://opencores.org/projects/ecpu_alu|ecpu_alu]]\\
+[[https://opencores.org/projects/edge|Edge Processor (MIPS)]]\\
+[[https://opencores.org/projects/mips_16|Educational 16-bit MIPS Processor]]\\
+[[https://opencores.org/projects/erp|Educational RISC Processor]]\\
+[[https://opencores.org/projects/elm|ELM Embedded Processor]]\\
+[[https://opencores.org/projects/erm16|erm16]]\\
+[[https://opencores.org/projects/fwrisc|Featherweight RISC-V]]\\
+[[https://opencores.org/projects/fluid_core_2|Fluid Core (A Reconfigurable Pipelined RISC processor)]]\\
+[[https://opencores.org/projects/myforthprocessor|FORTH processor with Java compiler]]\\
+[[https://opencores.org/projects/fpz8|FPz8]]\\
+[[https://opencores.org/projects/gpu|GPU]]\\
+[[https://opencores.org/projects/gup|HC11 Compatible - Gator uProcessor]]\\
+[[https://opencores.org/projects/hd63701|HD63701 compatible core]]\\
+[[https://opencores.org/projects/hf-risc|HF-RISC]]\\
+[[https://opencores.org/projects/hicovec|HiCoVec - a configurable SIMD CPU]]\\
+[[https://opencores.org/projects/hive|HIVE - a 32 bit, 8 thread, 4 register/stack hybrid, pipelined verilog soft processor core]]\\
+[[https://opencores.org/projects/hpc-16|HPC-16]]\\
+[[https://opencores.org/projects/hmta|HyperMTA]]\\
+[[https://opencores.org/projects/i650|i650]]\\
+[[https://opencores.org/projects/am9080_cpu_based_on_microcoded_am29xx_bit-slices|i8080 compatible processor using Am29XX bit slice family and microcoded design]]\\
+[[https://opencores.org/projects/ion|Ion - MIPS(tm) compatible CPU]]\\
+[[https://opencores.org/projects/jop|JOP: a Java Optimized Processor]]\\
+[[https://opencores.org/projects/k68|K68]]\\
+[[https://opencores.org/projects/klc32|KLC32]]\\
+[[https://opencores.org/projects/lattice6502|Lattice 6502]]\\
+[[https://opencores.org/projects/lem1_9min|LEM1_9]]\\
+[[https://opencores.org/projects/leros32|Leros-32]]\\
+[[https://opencores.org/projects/leros|Leros: A Tiny Microcontroller for FPGAs]]\\
+[[https://opencores.org/projects/light52|Lightweight 8051 compatible CPU]]\\
+[[https://opencores.org/projects/light8080|Lightweight 8080 compatible core]]\\
+[[https://opencores.org/projects/lpu|LocationPU]]\\
+\\
+[[https://opencores.org/projects/lxp32|LXP32, a lightweight 32-bit CPU core]]\\
+[[https://opencores.org/projects/m1_core|M1 Core]]\\
+[[https://opencores.org/projects/m32632|M32632 32-bit Processor]]\\
+[[https://opencores.org/projects/m65c02|M65C02]]\\
+[[https://opencores.org/projects/mblite|MB-Lite]]\\
+[[https://opencores.org/projects/mc6803|MC6803/6801 CPU]]\\
+[[https://opencores.org/projects/marca|McAdam's RISC Computer Architecture]]\\
+[[https://opencores.org/projects/mcip_open|MCIP open]]\\
+[[https://opencores.org/projects/mcpu|MCPU - A minimal CPU for a CPLD]]\\
+[[https://opencores.org/projects/microprocessor|microprocessor za208]]\\
+[[https://opencores.org/projects/microriscii|MicroRISC II]]\\
+[[https://opencores.org/projects/usimplez|MicroSimplez]]\\
+[[https://opencores.org/projects/minirisc|Mini-Risc core]]\\
+[[https://opencores.org/projects/pdp8l|Minimal PDP8/L implementation with 4K disk monitor system]]\\
+[[https://opencores.org/projects/minimips|miniMIPS]]\\
+[[https://opencores.org/projects/minimips_superscalar|miniMIPS Superscalar]]\\
+[[https://opencores.org/projects/octagon|mips compatible barrel processor]]\\
+[[https://opencores.org/projects/mips_fault_tolerant|Mips-FaultTolerant]]\\
+[[https://opencores.org/projects/mips32r1|MIPS32 Release 1]]\\
+[[https://opencores.org/projects/mips32_r1|MIPS32 Release 1 with support for FPU and other COPs]]\\
+[[https://opencores.org/projects/mips789|mips789]]\\
+[[https://opencores.org/projects/mipsr2000|mipsr2000]]\\
+[[https://opencores.org/projects/mips_enhanced|MIPS_enhanced]]\\
+[[https://opencores.org/projects/mmu180|MMU for Z80 and eZ80]]\\
+[[https://opencores.org/projects/mpx|MPX 32-bit CPU]]\\
+[[https://opencores.org/projects/msp430_vhdl|MSP430 CPU core in VHDL]]\\
+[[https://opencores.org/projects/myblaze|myBlaze]]\\
+[[https://opencores.org/projects/nanoblaze|NanoBlaze: the expandable processor]]\\
+[[https://opencores.org/projects/natalius_8bit_risc|Natalius 8 bit RISC]]\\
+[[https://opencores.org/projects/navre|Navré AVR clone (8-bit RISC)]]\\
+[[https://opencores.org/projects/ncore|nCore]]\\
+\\
+[[https://opencores.org/projects/neo430|NEO430 Processor (MSP430-compatible)]]\\
+[[https://opencores.org/projects/next186|Next 80186 processor]]\\
+[[https://opencores.org/projects/nextz80|NextZ80]]\\
+[[https://opencores.org/projects/odess_multicore_project|ODESS Multicore Project]]\\
+[[https://opencores.org/projects/oks8|oks8]]\\
+[[https://opencores.org/projects/oops|OoOPs - Out-of-Order MIPS (TM) Processor]]\\
+[[https://opencores.org/projects/open8_urisc|Open8 uRISC]]\\
+[[https://opencores.org/projects/oc54x|OpenCores54x DSP]]\\
+[[https://opencores.org/projects/opencpu|opencpu]]\\
+[[https://opencores.org/projects/opencpu32|OpenCPU32]]\\
+[[https://opencores.org/projects/openfire_core|OpenFire Processor Core]]\\
+\\
+[[https://opencores.org/projects/openmsp430|openMSP430]]\\
+\\
+[[https://opencores.org/projects/or1k|OpenRISC 1000]]\\
+[[https://opencores.org/projects/or1k_old|OpenRISC 1000 (old)]]\\
+[[https://opencores.org/projects/or1200_hp|OpenRisc 1200 HP, Hyper Pipelined OR1200 Core]]\\
+\\
+[[https://opencores.org/projects/or2k|OpenRISC 2000]]\\
+[[https://opencores.org/projects/open_source_tensor_like_processor_for_fpga_prototyping|OpenTPULike]]\\
+[[https://opencores.org/projects/p16c5x|P16C5x]]\\
+[[https://opencores.org/projects/pavr|pAVR]]\\
+[[https://opencores.org/projects/w11|PDP-11/70 CPU core and SoC]]\\
+[[https://opencores.org/projects/pdp8|PDP-8 Processor Core and System]]\\
+[[https://opencores.org/projects/pepelatz_misc|Pepelatz MISC]]\\
+\\
+[[https://opencores.org/projects/plasma|Plasma - most MIPS I(TM) opcodes]]\\
+[[https://opencores.org/projects/plasma_fpu|plasma with FPU]]\\
+[[https://opencores.org/projects/potato|Potato Processor]]\\
+[[https://opencores.org/projects/ppx16|PPX16 mcu]]\\
+[[https://opencores.org/projects/qrisc32|qrisc32 wishbone compatible risc core]]\\
+[[https://opencores.org/projects/quark|QUARK RISK]]\\
+[[https://opencores.org/projects/r2000|r2000 Soc]]\\
+[[https://opencores.org/projects/raptor64|Raptor64]]\\
+[[https://opencores.org/projects/avr8|Reduced AVR Core for CPLD]]\\
+[[https://opencores.org/projects/rois|Register Oriented Instruction Sets]]\\
+[[https://opencores.org/projects/riscmcu|RISC Microcontroller]]\\
+[[https://opencores.org/projects/risc16f84|risc16f84]]\\
+[[https://opencores.org/projects/risc5x|RISC5x]]\\
+[[https://opencores.org/projects/riscompatible|RISCOmpatible]]\\
+[[https://opencores.org/projects/risc_core_i|RISC_Core_I]]\\
+[[https://opencores.org/projects/rise|RISE Microprocessor]]\\
+[[https://opencores.org/projects/rtf65002|RTF65002]]\\
+[[https://opencores.org/projects/rtf8088|rtf8088]]\\
+[[https://opencores.org/projects/rv01_riscv_core|RV01 RISC-V core]]\\
+[[https://opencores.org/projects/s1_core|S1 Core]]\\
+[[https://opencores.org/projects/s80186|S80186]]\\
+[[https://opencores.org/projects/sayeh_processor|SAYEH educational processor]]\\
+[[https://opencores.org/projects/scarts|Scarts Processor]]\\
+[[https://opencores.org/projects/ssbcc|Small Stack Based Computer Compiler]]\\
+[[https://opencores.org/projects/sub86|Small x86 subset core]]\\
+[[https://opencores.org/projects/softavrcore|Soft AVR Core + Interfaces]]\\
+[[https://opencores.org/projects/wb4pb|Software Aided Wishbone Extension for Xilinx (R) PicoBlaze (TM)]]\\
+[[https://opencores.org/projects/steelcore|Steel Core]]\\
+[[https://opencores.org/projects/storm_core|Storm Core (ARM7 compatible)]]\\
+[[https://opencores.org/projects/sxp|SXP (Simple eXtensible Pipeline ) Processor]]\\
+[[https://opencores.org/projects/system11|system11]]\\
+[[https://opencores.org/projects/system68|System68]]\\
+\\
+[[https://opencores.org/projects/t400|T400 µController]]\\
+\\
+[[https://opencores.org/projects/t48|T48 µController]]\\
+[[https://opencores.org/projects/t51|T51 mcu]]\\
+[[https://opencores.org/projects/t65|T65 CPU]]\\
+[[https://opencores.org/projects/t6507lp|T6507LP]]\\
+[[https://opencores.org/projects/t80|T80 cpu]]\\
+[[https://opencores.org/projects/tg68|TG68 - execute 68000 Code]]\\
+[[https://opencores.org/projects/tg68kc|TG68K.C]]\\
+[[https://opencores.org/projects/neorv32|The NEORV32 Processor (RISC-V)]]\\
+[[https://opencores.org/projects/neptune-core|The Neptune Core]]\\
+[[https://opencores.org/projects/theia_gpu|Theia: ray graphic processing unit]]\\
+[[https://opencores.org/projects/thor|Thor Superscaler]]\\
+[[https://opencores.org/projects/tisc|Tiny Instruction Set Computer]]\\
+[[https://opencores.org/projects/tiny64|Tiny64]]\\
+[[https://opencores.org/projects/tiny8|tiny8]]\\
+[[https://opencores.org/projects/tinycpu|TinyCPU]]\\
+[[https://opencores.org/projects/tinyvliw8|tinyVLIW8]]\\
+[[https://opencores.org/projects/totalcpu|TotalCPU]]\\
+[[https://opencores.org/projects/turbo8051|turbo 8051]]\\
+[[https://opencores.org/projects/tv80|TV80]]\\
+[[https://opencores.org/projects/ucore|UCore]]\\
+[[https://opencores.org/projects/uos_processor|UoS Educational Processor]]\\
+[[https://opencores.org/projects/v586|v586]]\\
+[[https://opencores.org/projects/v6502|V6502]]\\
+[[https://opencores.org/projects/ic6821|vhdl core of IC6821]]\\
+[[https://opencores.org/projects/vliw_processor|VLIW Processor]]\\
+[[https://opencores.org/projects/vtach|VTACH - Bell Labs CARDIAC reimagined in Verilog]]\\
+[[https://opencores.org/projects/wishbone_bfm|Wishbone BFM]]\\
+[[https://opencores.org/projects/wb_z80|Wishbone High Performance Z80]]\\
+[[https://opencores.org/projects/y80e|Y80e - Z80/Z180 compatible processor extended by eZ80 instructions]]\\
+[[https://opencores.org/projects/yacc|YACC-Yet Another CPU CPU]]\\
+[[https://opencores.org/projects/yellowstar|Yellow Star]]\\
+[[https://opencores.org/projects/z3|Z3 - The Zork CPU]]\\
+[[https://opencores.org/projects/z80_vhdl|Z80 Soft Core Microprocessor]]\\
+[[https://opencores.org/projects/z80control|z80control]]\\
+[[https://opencores.org/projects/zap|ZAP]]\\
+[[https://opencores.org/projects/zet86|Zet - The x86 (IA-32) open implementation]]\\
+[[https://opencores.org/projects/zipcpu|Zip Cpu]]\\
+[[https://opencores.org/projects/zpu|ZPU - the worlds smallest 32 bit CPU with GCC toolchain]]\\