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page_zhenbang.liu [2019/04/17 16:07]
zhenbang [硬禾培训] 		page_zhenbang.liu [2019/06/21 17:30] (当前版本)
zhenbang
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 ### 硬禾培训 ### 硬禾培训
 +#### 培训后感受
 +[[page_zhenbang.liu_thinking|硬禾培训后感受]]
  
-[[yinghe_day1_ziyu|Day1 -- 2019.4.15]]+####​每日记录  ​
  
-[[yinghe_day2_ziyu|Day2 -- 2019.4.16]] 
  
-[[yinghe_day3_ziyu|Day3 -- 2019.4.17 项目三RISC-V在FPGA系统上的移植和功能演示 方案设计]] +[[DAY1]]   
-RISC-V在FPGA系统上的移植和功能演示 +[[DAY2]]   
---- +[[DAY3]]   
- +[[DAY4]]   
- +[[DAY5]]   
-项目参与人员及分工： +   
-  * [[学员1]] +    
-  ​* ​[[学员2]] +
-  * [[学员3]] +
- +
-### 项目需求 +
- +
---- +
- +
-#### 功能要求 +
-在STEP CYC10开发板上移植和仿真Reindeer RISC-V CPU软核，编写固件并基于STEP CYC10板设计功能板。 +
-#### 性能要求 +
- +
- - RISC－V的验证和仿真的改进 +
- - 设计基于STEP CYC10的功能扩展板以演示RISC-V系统 +
- - sketch for DRAM test +
- - Makefile for RISC-V +
- +
-#### 资源要求 +
-#### 进度要求 +
-#### 成本要求 +
-#### 其它要求 +
- +
-### 项目方案 +
- +
---- +
- +
-#### 方案综述： +
-#### 关键元器件： +
-#### 实施计划： +
- +
-### 项目实施 +
- +
---- +
-#### PCB设计 +
-#### PCB制造 +
-#### PCB焊接、调试 +
-#### FPGA连接和Verilog编程 +
-#### 系统测试 +
- +
-### 项目报告 +
- +
---- +
-#### 项目简要总结 +
-#### 项目达到的指标 +
-#### 项目改进及相应的方案 +
- +
-### 项目参考资料 +
- +
---- +
-#### 学习顺序 +
-  - 熟悉Intel Cyclone FPGA、Quartus Prime软件(Lattice MXO2 FPGA、Diamond软件)及FPGA设计流程 +
-  - 熟悉STEP CYC10开发板硬件资源 +
-  - 操作一遍FPGA + Arduino + 软核这种开发方式，[[http://​www.stepfpga.com/​doc/​reindeer_step|在小脚丫FPGA板上玩转开源农场（FARM）——FPGA+Arduino+RISC-V+Make]] +
-  - 看RISC-V相关资料，了解Reindeer_Step软核内部结构，对比FP-1T 8051软核，[[http://​www.stepfpga.com/​doc/​fpga_arduino_8051|基于FPGA使用Arduino编程的8051软核FP51-1T]]，主要参考外设IP ​ +
-  - 尝试修改Reindeer_Step外设并测试 +
-  - 尝试修改Reindeer Arduino IDE固件并测试 +
-  - 分工： +
-  * RISC－V的验证和仿真的改进 +
-  * 设计基于STEP CYC10的功能扩展板以演示RISC-V系统 +
-  * sketch for DRAM test +
-  * Makefile for RISC-V ​  +
- +
- +
-#### FPGA +
- +
-##### 硬件平台 +
-  - STEP FPGA核心板 +
-  - STEP CYC10开发板 +
- +
-##### 参考文档 +
- +
- ​- ​[1]   Intel Cyclone 10 LP Device Overview (C10LP51001),​ Intel Corporation,​ 05/​08/​2017 +
- ​- ​[2]   Intel Cyclone 10 LP Device Datasheet (C10LP51002),​ Intel Corporation,​ 05/​07/​2018 +
- - [3]   Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook (C10LP51003),​ Intel Corporation,​ 01/​24/​2019 +
- - [4]   ​UltraFast High-Level Productivity Design Methodology Guide, UG1197 (v2018.3) , Xilinx Inc., December 5, 2018 +
- - [5]   ​Building Embedded Systems, Programmable Hardware, Changyi Gu, Apress Media LLC, 02/2016 +
- - [6]   ​Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use?, Clifford E. Cummings and Don Mills, SNUG (Synopsys Users Group) San Jose, 2002 +
- - [7]   ​Asynchronous & Synchronous Reset Design Techniques - Part Deux, Clifford E. Cummings, Don Mills, Steve Golson, SNUG Boston 2003 +
- - [8]   A Review on Clock Gating Methodologies for power minimization in VLSI circuits， Harpreet Singh1, Dr. Sukhwinder Singh， International Journal of Scientific Engineering and Applied Science (IJSEAS) – Volume-2, Issue-1, January 2016 +
- - [9]   ​Crossing the abyss: asynchronous signals in a synchronous world, By Mike Stein, Paradigm Works, EDN Magazine, Jul 24, 2003 +
- - [10]  ​Keep metastability from killing your digital design, by Debora Grosse, Unisys, EDN Magazine, June 23, 1994 +
- - [11]  Practical design for transferring signals between clock domains, By Michael Crews and Yong Yuenyongsgool,​ Philips Semiconductors,​ EDN Magazine, Feb 20, 2003 +
- ​- ​[12]  ​Simulation and Synthesis Techniques for Asynchronous FIFO Design, Rev 1.2, Clifford E. Cummings, Sunburst Design, Inc., SNUG (Synopsys User Group Conference),​ San Jose, 2002 +
- - [13]  ​CMOS Digital Integrated Circuits - Analysis and Design (3rd Edition), Sung-Mo Kang, Yusuf Leblebici, McGraw-Hill Higher Education, 2003 +
- - [14]  Intel 8080 Microcomputer Systems user's Manual, Sep 1975 +
- - [15]  MC6800 8-bit Microprocessing Unit (MPU), Motorola Semiconductor Products Inc. 1984 +
- - [16]  M6800 Programming Reference Manual 1st Edition, Motorola, Inc. 1976 +
- - [17]  Verilog Digital Computer Design - Algorithms into Hardware, Mark Gordon Arnold, University of Wyoming, Prentice Hall PTR, 1999 +
- +
-#### RISV-V +
- +
- - Reindeer RISC-V CPU软核[[https://​github.com/​PulseRain/​Reindeer|Reindeer]]及[[https://​github.com/​PulseRain/​Reindeer_Step|Reindeer_Step]] +
- - [1]   ​RISC-V from Wikipedia (https://​en.wikipedia.org/​wiki/​RISC-V) +
- - [2]   ​RISC-V Geneology, Tony Chen and David A. Patterson, Electrical Engineering and Computer Sciences, University of California at Berkeley, Jan 24, 2016 +
- - [3]   ARM Kills Its RISC-V FUD Website After Staff Revolt，by Joel Hruska, EXTREMETECH Jul 12, 2018 +
- - [4]   ​PulseRain FP51-1T Microcontroller,​ Technical Reference Manual. (Doc#​TRM-0923-00001,​ Rev 1.0.0). PulseRain Technology, LLC, Sep 2017 +
- - [5]   The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2, Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, May 2017 +
- - [6]   The RISC-V Instruction Set Manual, Volume II: Privileged Architecture,​ Version 1.10, Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, May 2017 +
- - [7]   The RISC-V Reader: An Open Architecture Atlas, by David Patterson and Andrew Waterman, Strawberry Canyon, November 7, 2017 +
- - [8]   ​Design of the RISC-V Instruction Set Architecture,​ by Andrew Shell Waterman, A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley, Spring 2016 +
- - [9]   ​System and method for fusing instructions,​ Ronny Ronen, Alexander Peleg and Nathaniel Hoffman, Intel Corp, United States Patent No: US6675376B2,​ 12/​29/​2000 +
- - [10]  ARM Cortex-A Series Programmer’s Guide for ARMv8-A, Version: 1.0, ARM Limited, Mar 24, 2015 +
- - [11]  Building Embedded Systems, Programmable Hardware, Changyi Gu, Apress Media LLC, 02/2016 +
- - [12]  JEDEC from Wikipedia (https://​en.wikipedia.org/​wiki/​JEDEC) +
- +
-#### Reindeer RISC-V CPU移植 +
- +
- - [[http://​www.stepfpga.com/​doc/​reindeer_step|在小脚丫FPGA板上玩转开源农场（FARM）——FPGA+Arduino+RISC-V+Make]] +
- - [[http://​www.stepfpga.com/​doc/​fpga_arduino_8051|基于FPGA使用Arduino编程的8051软核FP51-1T]]+
  
 +[[WEEK2 DAY1]]  ​
 +[[WEEK2 DAY2]]  ​
 +[[WEEK2 DAY3]]  ​
 +[[WEEK2 DAY4]]  ​
 +[[WEEK2 DAY5]]  ​
 +[[WEEK2 DAY6]]  ​
 +  ​
 +[[WEEK3 DAY1]]  ​
 +[[WEEK3 DAY2]]  ​
 +[[WEEK3 DAY3]]  ​
 +[[WEEK3 DAY4]]  ​
 +[[WEEK3 DAY5]]  ​
 +  ​
 +[[WEEK4 DAY1]]  ​
 +[[WEEK4 DAY2]] ​  
 +[[WEEK4 DAY3]] ​  
 +[[WEEK4 DAY4]] ​  
 +[[WEEK4 DAY5]] ​  
 +[[WEEK4 DAY6]] ​  
 +[[WEEK4 DAY7]]  ​
 +  ​
 +    ​
  
 +[[WEEK5 DAY1]] ​  
 +[[WEEK5 DAY2]] ​  
 +[[WEEK5 DAY3]]  ​
 +[[WEEK5 DAY15]]  ​