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两侧同时换到之前的修订记录 前一修订版 后一修订版 | 前一修订版 | ||
fpga [2019/05/07 00:46] gongyu [主要的IP内核] |
fpga [2019/05/07 00:50] (当前版本) gongyu [主要的IP内核] |
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* [[https://opencores.org/projects?expanded=Uncategorized|未分类的开源代码]] | * [[https://opencores.org/projects?expanded=Uncategorized|未分类的开源代码]] | ||
* [[https://opencores.org/projects?expanded=Other|其它开源代码]] | * [[https://opencores.org/projects?expanded=Other|其它开源代码]] | ||
- | * [[ipcore_stepfpga|来自小脚丫官网上的IP内核]] | ||
* [[ipcore_fpga4fun|来自FPGA4FUN上的IP内核]] - fpga4fun是一个不错的FPGA学习网站,其网址为https://www.fpga4fun.com,在这个网站上有一些经过验证的项目的设计思路和源代码,可供FPGA爱好者参考。 | * [[ipcore_fpga4fun|来自FPGA4FUN上的IP内核]] - fpga4fun是一个不错的FPGA学习网站,其网址为https://www.fpga4fun.com,在这个网站上有一些经过验证的项目的设计思路和源代码,可供FPGA爱好者参考。 | ||
* 基础项目: | * 基础项目: | ||
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- [CUGA-1](http://hamsterworks.co.nz/mediawiki/index.php/CUGA-1): 使用门阵列的CPU * [Design&Reuse上的IP Core资源](https://www.design-reuse.com) | - [CUGA-1](http://hamsterworks.co.nz/mediawiki/index.php/CUGA-1): 使用门阵列的CPU * [Design&Reuse上的IP Core资源](https://www.design-reuse.com) | ||
* [icoboard.org](http://icoboard.org/verilog-projects.html)上面的[[VerilogOpenSource|Verilog开源资源]] | * [icoboard.org](http://icoboard.org/verilog-projects.html)上面的[[VerilogOpenSource|Verilog开源资源]] | ||
+ | * 通信相关 | ||
+ | * 业余高频[SDR收发模块](https://github.com/softerhardware/Hermes-Lite2)项目链接 | ||
+ | * [SDR的Verilog代码](https://github.com/TAPR/DCP6) | ||
+ | * [用Verilog编写的基于Cyclone III的VHF SDR接收器](https://github.com/marsohod4you/FPGA_SDR) | ||
+ | * [用Verilog编写的基于Cyclone III的FM Radiosender](https://github.com/marsohod4you/FPGA_FM_transmitter) | ||
+ | * 在github上的[无线电信号处理组件](http://ebrombaugh.studionebula.com/radio/iceRadio/index.html) | ||
+ | * [用Verilog实现的GPS接收器](http://www.aholme.co.uk/GPS/Main.htm) | ||
+ | * 音、视频相关 | ||
+ | * 声音合成器[OPL3](https://github.com/gtaylormb/opl3_fpga/tree/master/fpga/bd/opl3_cpu) | ||
+ | * [吉他效果引擎(VHDL)链接](https://github.com/Vladilit/fpga-multi-effect) | ||
+ | * [VGA摄像头模块OV7670接口](https://github.com/westonb/OV7670-Verilog) | ||
+ | * [VGA模式发生器](https://github.com/jbush001/FPGAWhack) | ||
+ | * [用VHDL写的H.264视频编码器](https://github.com/bcattle/hardh264) | ||
+ | * [用Verilog写的H.265视频编码器](https://github.com/Bearzeng/h.265_encoder) | ||
+ | * [将数码相机连接到PMOD](http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670) | ||
+ | * [用于MIPI显示的2D图形控制器](https://github.com/gtjennings1/UPDuino-LH154Q01-Display/tree/master/FPGA/source) | ||
+ | * [用于嵌入式MCU的2D图形控制器](http://andybrown.me.uk/2014/06/01/ase/) | ||
+ | * [JESD204B](https://github.com/m-labs/jesd204b)高速接口 | ||
+ | * [用Verilog实现的ieee 754浮点库](https://github.com/dawsonjon/fpu) | ||
+ | * RISC-V相关 | ||
+ | * [icoSoC Risc-V微控制器,在icoBoard上运行接口](https://github.com/cliffordwolf/icotools/tree/master/icosoc) | ||
+ | * [搭乘无序的Risc-V CPU](https://github.com/ridecore/ridecore/) | ||
+ | * [V-Scale Risc-V CPU实现](https://github.com/albert-magyar/vscale) | ||
+ | * [完整的32位Risc-V SoC,具有大量外设](https://github.com/pulp-platform/pulpino) | ||
+ | * [Risc-V CPU(来自Vectorblox)](https://github.com/VectorBlox/risc-v) | ||
+ | * 通用处理器 | ||
+ | * [用Verilog实现的Lisp MCU](https://github.com/jbush001/LispMicrocontroller) | ||
+ | * [Zip](http://opencores.org/project,zipcpu) CPU,一个用于FPGA的小型CPU | ||
+ | * [manycore SoC组件](http://www.optimsoc.org/index.html) | ||
+ | * [一个完整的CPU,SPI,VGA,串口](https://github.com/mattstock/bexkat1) | ||
+ | * [Bexkat1 32位CPU](https://hackaday.io/project/8716-bexkat1-cpu) | ||
+ | * [带游戏机的68000 CPU](https://github.com/neogeodev/NeoGeoFPGA-sim) | ||
+ | * [6502 CPU核心(Verilog)](https://github.com/Arlet/verilog-6502) | ||
+ | * [M32632 32位CPU(Verilog)](http://opencores.org/project,m32632) | ||
+ | * [GPU](https://github.com/jbush001/NyuziProcessor) | ||
+ | * [一个开源的Verilog GPU实现(不适合icoBoard)和描述](https://github.com/HeavyPixels/QuickSilverNEO) | ||
+ | * [许多完整的传统家庭计算机系统在Verilog中实现,如Acorn Archimedes](https://github.com/mist-devel/mist-board/tree/master/cores) | ||
+ | * [一个带调试器连接的小型CPU](https://github.com/atgreen/moxie-cores) | ||
+ | * [Amstrad家用电脑仿真器(VHDL版)](http://www.cpcwiki.eu/index.php/FPGAmstrad) | ||
+ | * 存储器管理 | ||
+ | * [SDRAM控制器](https://github.com/stffrdhrn/sdram-controller) | ||
+ | * [用于SDRAM控制器的Verilog代码](http://ladybug.xs4all.nl/arlet/fpga/source/sdram.v) | ||
+ | * [用在小容量FPGA上的SDRAM控制器(VHDL)的Verilog代码](http://hackaday.com/2013/10/11/sdram-controller-for-low-end-fpgas/) | ||
+ | * 测量相关 | ||
+ | * 基于FPGA的逻辑分析仪 - [Sump2](https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/) | ||
+ | * 其它 | ||
+ | * [不用乘法器的乘法FFT和FIR Verilog发生器](http://www.spiral.net/hardware.html) | ||
+ | * [用于10 GBit以太网的TCP/IP协议栈](https://github.com/dsidler/fpga-network-stack) | ||
+ | * [SATA for Elphel Camera项目](http://blog.elphel.com/2016/03/free-fpga-reimplement-the-primitives-models/#more-6655) | ||
+ | * [AXI总线开源实现(Xilinx上的SystemVerilog)](http://blog.dspia.com/2015/08/05/open-source-axi3-bus-functional-model-bfm/) | ||
+ | * [一些FPGA项目,如带有Verilog源代码的PMOD(似乎是VHDL)](http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects) | ||
+ | * [频率计数器](http://www.circuitvalley.com/2015/10/simple-frequency-meter-counter-fpga-xilinx-altera-cpld-wireframe.html) | ||
+ | * [数字伺服](https://github.com/nist-ionstorage/digital-servo) | ||
+ | * [I2S输出(VHDL)](http://hamsterworks.co.nz/mediawiki/index.php/PMODamp3) | ||
+ | * [FPGA中的浮点数学(VHDL生成器)](http://flopoco.gforge.inria.fr/) | ||
+ | * [红外接收器](https://github.com/circuitvalley/WireFrame-FPGA/tree/master/VerilogHDL-Modules/Nec_Decoder) | ||
+ | * [小型游戏机,模拟CPU上的游戏](https://fotino.me/consolite-fpga/) | ||
+ | * [CMAC使用AES作为分组密码来键控散列函数](https://github.com/secworks/cmac) | ||
* [[ipcore_lattice|来自Lattice官网的IP内核]]{{:psg_2019_i0211k_rev20.pdf|IP内核参考指南}} | * [[ipcore_lattice|来自Lattice官网的IP内核]]{{:psg_2019_i0211k_rev20.pdf|IP内核参考指南}} | ||
* [[ipcore_altera|来自Altera/Intel官网上的IP内核]], 其官网上提供的{{:intel-intellectual-property-brochure.pdf|IP内核参考指南}} | * [[ipcore_altera|来自Altera/Intel官网上的IP内核]], 其官网上提供的{{:intel-intellectual-property-brochure.pdf|IP内核参考指南}} | ||
+ | * [[ipcore_stepfpga|来自小脚丫官网上的IP内核]] | ||
更多关于FPGA的资料和学习案例参见[[stepfpga|小脚丫FPGA学习]] | 更多关于FPGA的资料和学习案例参见[[stepfpga|小脚丫FPGA学习]] |