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fpga4students上fpga相关的项目 [2019/04/25 16:49] jingjing |
fpga4students上fpga相关的项目 [2020/07/30 10:31] (当前版本) zili |
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| ===== fpga4students上fpga相关的项目 ===== | ===== fpga4students上fpga相关的项目 ===== | ||
| - | 1. [[|什么是FPGA？FPGA如何工作？]] | + | 1. [[https://www.fpga4student.com/2016/12/what-is-fpga-five-reasons-why-i-love-fpga.html|什么是FPGA？FPGA如何工作？]] |
| - | 2. [[|Basys 3 FPGA OV7670相机]] | + | 2. [[https://www.fpga4student.com/2018/08/basys-3-fpga-ov7670-camera.html|Basys 3 FPGA OV7670相机]] |
| - | 3. [[|如何将文本文件或图像加载到FPGA中]] | + | 3. [[https://www.fpga4student.com/2016/11/two-ways-to-load-text-file-to-fpga-or.html|如何将文本文件或图像加载到FPGA中]] |
| - | 4. [[|使用Verilog在FPGA上进行图像处理]] | + | 4. [[https://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html|使用Verilog在FPGA上进行图像处理]] |
| - | 5. [[|FPGA上的车牌识别]] | + | 5. [[https://www.fpga4student.com/2016/11/plate-license-recognition-verilogmatlab.html|FPGA上的车牌识别]] |
| - | 6. [[|使用Verilog在FPGA上的闹钟]] | + | 6. [[https://www.fpga4student.com/2016/11/verilog-code-for-alarm-clock-on-fpga.html|使用Verilog在FPGA上的闹钟]] |
| - | 7. [[|使用VHDL在FPGA上的数字时钟]] | + | 7. [[https://www.fpga4student.com/2016/11/vhdl-code-for-digital-clock-on-fpga.html|使用VHDL在FPGA上的数字时钟]] |
| - | 8. [[|用于在FPGA上去抖按钮的简单Verilog代码]] | + | 8. [[https://www.fpga4student.com/2017/04/simple-debouncing-verilog-code-for.html|用于在FPGA上去抖按钮的简单Verilog代码]] |
| - | 9. [[|FPGA上的红绿灯控制器]] | + | 9. [[https://www.fpga4student.com/2016/11/verilog-code-for-traffic-light-system.html|FPGA上的红绿灯控制器]] |
| - | 10. [[|Verilog中FPGA上的停车系统]] | + | 10. [[https://www.fpga4student.com/2016/11/verilog-code-for-parking-system-using.html|Verilog中FPGA上的停车系统]] |
| - | 11. [[|用于FPGA上的比较器的VHDL代码]] | + | 11. [[https://www.fpga4student.com/2016/11/verilog-code-for-8-bit-74f521-identity.html|用于FPGA上的比较器的VHDL代码]] |
| - | 12. [[|FPGA上的乘法器的Verilog代码]] | + | 12. [[https://www.fpga4student.com/2016/11/verilog-code-for-4x4-multiplier-using.html|FPGA上的乘法器的Verilog代码]] |
| - | 13. [[|FPGA上的VHDL中的N位环形计数器]] | + | 13. [[https://www.fpga4student.com/2016/11/programmable-n-bit-switch-tail-ring.html|FPGA上的VHDL中的N位环形计数器]] |
| - | 14. [[|在FPGA上实现微控制器的Verilog]] | + | 14. [[https://www.fpga4student.com/2016/11/verilog-code-for-microcontroller.html|在FPGA上实现微控制器的Verilog]] |
| - | 15. [[|Verilog在FPGA上携带前瞻性倍增器]] | + | 15. [[https://www.fpga4student.com/2016/11/verilog-code-for-carry-look-ahead-multiplier.html|Verilog在FPGA上携带前瞻性倍增器]] |
| - | 16. [[|FPGA Xilinx上的VHDL矩阵乘法]] | + | 16. [[https://www.fpga4student.com/2016/11/matrix-multiplier-core-design.html|FPGA Xilinx上的VHDL矩阵乘法]] |
| - | 17. [[|使用Verilog在FPGA上定点矩阵乘法]] | + | 17. [[https://www.fpga4student.com/2016/12/fixed-point-matrix-multiplication-in-Verilog.html|使用Verilog在FPGA上定点矩阵乘法]] |
| - | 18. [[|FPGA上的Verilog Divider]] | + | 18. [[https://www.fpga4student.com/2016/12/32-bit-unsigned-divider-in-verilog.html|FPGA上的Verilog Divider]] |
| - | 19. [[|用于FPGA上的微控制器的VHDL代码]] | + | 19. [[https://www.fpga4student.com/2016/12/a-complete-8-bit-microcontroller-in-vhdl.html|用于FPGA上的微控制器的VHDL代码]] |
| - | 20. [[|用于FPGA上FIR滤波器的VHDL代码]] | + | 20. [[https://www.fpga4student.com/2017/01/a-low-pass-fir-filter-in-vhdl.html|用于FPGA上FIR滤波器的VHDL代码]] |
| - | 21. [[|FPGA上数字逻辑组件的Verilog代码]] | + | 21. [[https://www.fpga4student.com/2017/01/basic-digital-blocks-in-verilog.html|FPGA上数字逻辑组件的Verilog代码]] |
| - | 22. [[|使用Verilog在FPGA上实现延迟定时器]] | + | 22. [[https://www.fpga4student.com/2017/01/programmable-digital-delay-timer-in-Verilog.html|使用Verilog在FPGA上实现延迟定时器]] |
| - | 23. [[|使用Verilog的FPGA上的单周期MIPS处理器]] | + | 23. [[https://www.fpga4student.com/2017/01/verilog-code-for-single-cycle-MIPS-processor.html|使用Verilog的FPGA上的单周期MIPS处理器]] |
| - | 24. [[|FPGA上的FIFO Verilog实现]] | + | 24. [[https://www.fpga4student.com/2017/01/verilog-code-for-fifo-memory.html|FPGA上的FIFO Verilog实现]] |
| - | 25. [[|FPGA上的FIFO VHDL实现]] | + | 25. [[https://www.fpga4student.com/2017/01/vhdl-code-for-fifo-memory.html|FPGA上的FIFO VHDL实现]] |
| - | 26. [[|FPGA上的Verilog D触发器]] | + | 26. [[https://www.fpga4student.com/2017/02/verilog-code-for-d-flip-flop.html|FPGA上的Verilog D触发器]] |
| - | 27. [[|使用Verilog的FPGA比较器设计]] | + | 27. [[https://www.fpga4student.com/2017/02/verilog-code-for-comparator.html|使用Verilog的FPGA比较器设计]] |
| - | 28. [[|使用VHDL在FPGA上进行D触发器]] | + | 28. [[https://www.fpga4student.com/2017/02/vhdl-code-for-d-flip-flop.html|使用VHDL在FPGA上进行D触发器]] |
| - | 29. [[|使用Verilog在FPGA上进行全加器设计]] | + | 29. [[https://www.fpga4student.com/2017/02/verilog-code-for-full-adder.html|使用Verilog在FPGA上进行全加器设计]] |
| - | 30. [[|使用VHDL在FPGA上进行全加器设计]] | + | 30. [[https://www.fpga4student.com/2017/02/vhdl-code-for-full-adder.html|使用VHDL在FPGA上进行全加器设计]] |
| - | 31. [[|使用Verilog Testbench的FPGA计数器]] | + | 31. [[https://www.fpga4student.com/2017/03/verilog-code-for-counter-with-testbench.html|使用Verilog Testbench的FPGA计数器]] |
| - | 32. [[|使用Verilog在FPGA上进行RISC处理器设计]] | + | 32. [[https://www.fpga4student.com/2017/04/verilog-code-for-16-bit-risc-processor.html|使用Verilog在FPGA上进行RISC处理器设计]] |
| - | 33. [[|用于FPGA上输入端口的Verilog测试平台]] | + | 33. [[https://www.fpga4student.com/2017/05/how-to-write-verilog-testbench-for.html|用于FPGA上输入端口的Verilog测试平台]] |
| - | 34. [[|使用VHDL的FPGA上的PWM发生器]] | + | 34. [[https://www.fpga4student.com/2017/06/pwm-generator-in-vhdl.html|使用VHDL的FPGA上的PWM发生器]] |
| - | 35. [[|使用Verilog在FPGA上进行Tic Tac Toe游戏]] | + | 35. [[https://www.fpga4student.com/2017/06/tic-tac-toe-game-in-verilog-and-logisim.html|使用Verilog在FPGA上进行Tic Tac Toe游戏]] |
| - | 36. [[|用于ALU的FPGA的VHDL代码]] | + | 36. [[https://www.fpga4student.com/2017/06/vhdl-code-for-arithmetic-logic-unit-alu.html|用于ALU的FPGA的VHDL代码]] |
| - | 37. [[|用于ALU的FPGA的Verilog代码]] | + | 37. [[https://www.fpga4student.com/2017/06/Verilog-code-for-ALU.html|用于ALU的FPGA的Verilog代码]] |
| - | 38. [[|采用VHDL测试平台的FPGA上的计数器设计]] | + | 38. [[https://www.fpga4student.com/2017/06/vhdl-code-for-counters-with-testbench.html|采用VHDL测试平台的FPGA上的计数器设计]] |
| - | 39. [[|Verilog中基于FPGA的流水线MIPS处理器（第1部分）]] | + | 39. [[https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-1.html|Verilog中基于FPGA的流水线MIPS处理器（第1部分）]] |
| - | 40. [[|Verilog中基于FPGA的流水线MIPS处理器（第2部分）]] | + | 40. [[https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-2.html|Verilog中基于FPGA的流水线MIPS处理器（第2部分）]] |
| - | 41. [[|Verilog中基于FPGA的流水线MIPS处理器（第3部分）]] | + | 41. [[https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-3.html|Verilog中基于FPGA的流水线MIPS处理器（第3部分）]] |
| - | 42. [[|FPGA上的Verilog解码器]] | + | 42. [[https://www.fpga4student.com/2017/07/verilog-code-for-decoder.html|FPGA上的Verilog解码器]] |
| - | 43. [[|FPGA上的Verilog多路复用器]] | + | 43. [[https://www.fpga4student.com/2017/07/verilog-code-for-multiplexers.html|FPGA上的Verilog多路复用器]] |
| - | 44. [[|Verilog中FPGA上的N位加法器设计]] | + | 44. [[https://www.fpga4student.com/2017/07/n-bit-adder-design-in-verilog.html|Verilog中FPGA上的N位加法器设计]] |
| - | 45. [[|使用N位Verilog加法器的FPGA上的VHDL ALU]] | + | 45. [[https://www.fpga4student.com/2017/07/16-bit-alu-design-in-vhdl.html|使用N位Verilog加法器的FPGA上的VHDL ALU]] |
| - | 46. [[|FPGA上的VHDL移位器]] | + | 46. [[https://www.fpga4student.com/2017/07/shifter-design-in-vhdl.html|FPGA上的VHDL移位器]] |
| - | 47. [[|在FPGA上查找表VHDL示例代码]] | + | 47. [[https://www.fpga4student.com/2017/07/non-linear-lookup-table-implementation.html|在FPGA上查找表VHDL示例代码]] |
| - | 48. [[|FPGA上的协处理器VHDL实现]] | + | 48. [[https://www.fpga4student.com/2017/07/cryptographic-coprocessor-design-in-vhdl.html|FPGA上的协处理器VHDL实现]] |
| - | 49. [[|适合初学者的经济实惠的Xilinx FPGA板卡]] | + | 49. [[https://www.fpga4student.com/2017/07/recommended-affordable-Xilinx-FPGA-boards-for-students.html|适合初学者的经济实惠的Xilinx FPGA板卡]] |
| - | 50. [[|适合初学者的经济型Altera FPGA板卡]] | + | 50. [[https://www.fpga4student.com/2017/08/recommended-affordable-Altera-FPGA-boards-for-students.html|适合初学者的经济型Altera FPGA板卡]] |
| - | 51. [[|什么是FPGA编程？]] | + | 51. [[https://www.fpga4student.com/2017/08/what-is-fpga-programming.html|什么是FPGA编程？]] |
| - | 52. [[|Verilog与VHDL：通过实例解释]] | + | 52. [[https://www.fpga4student.com/2017/08/verilog-vs-vhdl-explain-by-example.html|Verilog与VHDL：通过实例解释]] |
| - | 53. [[|FPGA上时钟分频器的VHDL代码]] | + | 53. [[https://www.fpga4student.com/2017/08/vhdl-code-for-clock-divider-on-fpga.html|FPGA上时钟分频器的VHDL代码]] |
| - | 54. [[|FPGA上时钟分频器的Verilog代码]] | + | 54. [[https://www.fpga4student.com/2017/08/verilog-code-for-clock-divider-on-fpga.html|FPGA上时钟分频器的Verilog代码]] |
| - | 55. [[|如何生成时钟使能信号而不是创建另一个时钟域]] | + | 55. [[https://www.fpga4student.com/2017/08/how-to-generate-clock-enable-signal.html|如何生成时钟使能信号而不是创建另一个时钟域]] |
| - | 56. [[|用于在FPGA上对按钮进行去抖动的VHDL代码]] | + | 56. [[https://www.fpga4student.com/2017/08/vhdl-code-for-debouncing-buttons-on-fpga.html|用于在FPGA上对按钮进行去抖动的VHDL代码]] |
| - | 57. [[|用于FPGA上交通灯控制器的VHDL代码]] | + | 57. [[https://www.fpga4student.com/2017/08/vhdl-code-for-traffic-light-controller.html|用于FPGA上交通灯控制器的VHDL代码]] |
| - | 58. [[|FPGA上PWM发生器的Verilog代码]] | + | 58. [[https://www.fpga4student.com/2017/08/verilog-code-for-pwm-generator.html|FPGA上PWM发生器的Verilog代码]] |
| - | 59. [[|用于FPGA上的简单2位比较器的VHDL代码]] | + | 59. [[https://www.fpga4student.com/2017/08/vhdl-code-for-comparator.html|用于FPGA上的简单2位比较器的VHDL代码]] |
| - | 60. [[|单端口RAM的VHDL代码]] | + | 60. [[https://www.fpga4student.com/2017/08/vhdl-code-for-single-port-ram.html|单端口RAM的VHDL代码]] |
| - | 61. [[|使用有限状态机（FSM）的VHDL FPGA车辆停放系统]] | + | 61. [[https://www.fpga4student.com/2017/08/car-parking-system-in-vhdl-using-FSM.html|使用有限状态机（FSM）的VHDL FPGA车辆停放系统]] |
| - | 62. [[|MIPS处理器的VHDL代码]] | + | 62. [[https://www.fpga4student.com/2017/09/vhdl-code-for-mips-processor.html|MIPS处理器的VHDL代码]] |
| - | 63. [[|使用Moore FSM的序列检测器的Verilog代码]] | + | 63. [[https://www.fpga4student.com/2017/09/verilog-code-for-moore-fsm-sequence-detector.html|使用Moore FSM的序列检测器的Verilog代码]] |
| - | 64. [[|使用Moore FSM的序列检测器的完整VHDL代码]] | + | 64. [[https://www.fpga4student.com/2017/09/vhdl-code-for-moore-fsm-sequence-detector.html|使用Moore FSM的序列检测器的完整VHDL代码]] |
| - | 65. [[|[FPGA教程] Basys 3 FPGA上的七段LED显示控制器]] | + | 65. [[https://www.fpga4student.com/2017/09/seven-segment-led-display-controller-basys3-fpga.html|[FPGA教程] Basys 3 FPGA上的七段LED显示控制器]] |
| - | 66. [[|Basys 3 FPGA上七段显示的VHDL代码]] | + | 66. [[https://www.fpga4student.com/2017/09/vhdl-code-for-seven-segment-display.html|Basys 3 FPGA上七段显示的VHDL代码]] |
| - | 67. [[|[FPGA教程]如何将鼠标与Basys 3 FPGA接口]] | + | 67. [[https://www.fpga4student.com/2017/12/how-to-interface-mouse-with-FPGA.html|[FPGA教程]如何将鼠标与Basys 3 FPGA接口]] |
| - | 68. [[|Rilry Carry Adder的Verilog代码]] | + | 68. [[https://www.fpga4student.com/2018/07/verilog-code-for-ripple-carry-adder.html|Rilry Carry Adder的Verilog代码]] |
| - | 69. [[|如何使用VHDL将图像读入FPGA]] | + | 69. [[https://www.fpga4student.com/2018/08/how-to-read-image-in-vhdl.html|如何使用VHDL将图像读入FPGA]] |