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温度计 [2017/03/13 14:52]
zhijun 		温度计 [2021/08/18 09:00] (当前版本)
gongyusu
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-======基于小脚丫STEP MXO2的温度显示系统====== +## 基于小脚丫STEP MXO2的温度显示系统 
-=====一、项目简介=====+ 
 +### 1、项目简介
 基于小脚丫STEP MXO2的温度显示系统的核心控制模块为小脚丫STEP MXO2开发板，采用由MicroUSB输入的5V供电，温度传感器选用的是DALLAS的经典传感器——DS18B20，一个封装和常见三极管（TO-92）相同的温度传感器，而显示模块采用LCD1602，相信读者对这两个模块一定是极为熟悉。 基于小脚丫STEP MXO2的温度显示系统的核心控制模块为小脚丫STEP MXO2开发板，采用由MicroUSB输入的5V供电，温度传感器选用的是DALLAS的经典传感器——DS18B20，一个封装和常见三极管（TO-92）相同的温度传感器，而显示模块采用LCD1602，相信读者对这两个模块一定是极为熟悉。
  
-=====二、项目框图=====+--- 
 + 
 +### 2、项目框图
 {{ ::​框图.png ?600 |}} {{ ::​框图.png ?600 |}}
-====1.控制核心====+ 
 +#### 2.1 控制核心 
 温度计项目控制核心为小脚丫STEP MXO2 V2版本FPGA开发板，FPGA芯片为Lattice Semiconductor的MachXO2 400HC系列FPGA。 温度计项目控制核心为小脚丫STEP MXO2 V2版本FPGA开发板，FPGA芯片为Lattice Semiconductor的MachXO2 400HC系列FPGA。
-====2.温度采集模块====+ 
 +#### 2.2 温度采集模块
 温度采集模块采用Dallas的经典产品——DS18B20，是一个高精度，占用空间小，硬件连接简单，价格低廉的数字温度传感器，采用单总线驱动方式，更为节省开发板资源。 温度采集模块采用Dallas的经典产品——DS18B20，是一个高精度，占用空间小，硬件连接简单，价格低廉的数字温度传感器，采用单总线驱动方式，更为节省开发板资源。
-====3.温度显示系统====+ 
 +#### 2.3 温度显示系统
 温度显示模块采用集成了ASCII字库的LCD1602，省去了自建字库的麻烦。 温度显示模块采用集成了ASCII字库的LCD1602，省去了自建字库的麻烦。
  
-=====三、硬件电路图=====+--- 
 +### 3、硬件电路图
 {{ ::​电路图.png?​800 |}} {{ ::​电路图.png?​800 |}}
 温度计的硬件电路比较简单，首先在供电方面，作为控制核心的小脚丫开发板由于具备完善的下载与供电方案，故不必在设计下载电路，只需要一根MicroUSB数据线即可满足整体系统的供电与下载； 温度计的硬件电路比较简单，首先在供电方面，作为控制核心的小脚丫开发板由于具备完善的下载与供电方案，故不必在设计下载电路，只需要一根MicroUSB数据线即可满足整体系统的供电与下载；
-\\+
 在温度采集部分，DS18B20共有三个引脚，我们参照硬件手册，可发现该芯片的1号引脚接地，2号引脚为数据信号DQ，接到小脚丫的任意引脚上（下图接到了小脚丫STEP MXO2的“SI”引脚上），3号引脚为电源脚，参照手册，DS18B20的输入电压为3.0V-5.5V，此处我们采用了3.3V供电。 在温度采集部分，DS18B20共有三个引脚，我们参照硬件手册，可发现该芯片的1号引脚接地，2号引脚为数据信号DQ，接到小脚丫的任意引脚上（下图接到了小脚丫STEP MXO2的“SI”引脚上），3号引脚为电源脚，参照手册，DS18B20的输入电压为3.0V-5.5V，此处我们采用了3.3V供电。
-\\+
 温度显示部分，LCD1602共有16个引脚，下图为LCD1602的引脚简介，对应连接即可： 温度显示部分，LCD1602共有16个引脚，下图为LCD1602的引脚简介，对应连接即可：
 {{ ::​lcd1602引脚定义.png?​400 |}} {{ ::​lcd1602引脚定义.png?​400 |}}
  
-=====四、Verilog代码===== +--- 
-====Verilog代码==== +### 4、Verilog代码
------- +
-<code verilog>+
  
 +#### 4.1 Verilog代码:​LCD1602显示部分
 +<code verilog>
 // -------------------------------------------------------------------- // --------------------------------------------------------------------
 // >>>>>>>>>>>>>>>>>>>>>>>>>​ COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<​ // >>>>>>>>>>>>>>>>>>>>>>>>>​ COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<​
行 194: 行 202:
  endcase   endcase
  end  ​  end  ​
- 
  
 //​-------------------------------------//​ //​-------------------------------------//​
行 392: 行 399:
 end end
     ​     ​
- 
 endmodule endmodule
- 
-  
- 
  
 </​code>​ </​code>​
  
 +---
 +#### 4.2 温度采集部分
 +<code verilog>
 +// --------------------------------------------------------------------
 +// >>>>>>>>>>>>>>>>>>>>>>>>>​ COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<​
 +// --------------------------------------------------------------------
 +// Module:​DS18B20Z ​
 +// 
 +// Author: Step
 +// 
 +// Description:​ Drive DS18B20Z to get temperature code
 +// 
 +// Web: www.stepfpga.com
 +// 
 +// --------------------------------------------------------------------
 +// Code Revision History :
 +// --------------------------------------------------------------------
 +// Version: |Mod. Date:   ​|Changes Made:
 +// V1.0     ​|2015/​11/​11 ​  ​|Initial ver
 +// --------------------------------------------------------------------
 +module DS18B20Z
 +(
 + input clk_in,​ //​ system clock
 + input rst_n_in,​ //​ system reset, active low
 + inout one_wire,​ //​ ds18b20z one-wire-bus
 + output reg [15:​0] data_out //​ ds18b20z data_out
 +);
 +
  
 +    
 +
 + localparam IDLE = 3'​d0;​
 + localparam MAIN = 3'​d1;​
 + localparam INIT = 3'​d2;​
 + localparam WRITE = 3'​d3;​
 + localparam READ = 3'​d4;​
 + localparam DELAY = 3'​d5;​
 +
 + //generate clk_1mhz clock
 + reg clk_1mhz;​
 + reg [2:​0] cnt_1mhz;​
 + always@(posedge clk_in or negedge rst_n_in) begin
 + if(!rst_n_in) begin
 + cnt_1mhz <= 3'd0;
 + clk_1mhz <= 1'b0;
 + end else if(cnt_1mhz >= 3'd5) begin
 + cnt_1mhz <= 3'd0;
 + clk_1mhz <= ~clk_1mhz;
 + end else begin
 + cnt_1mhz <= cnt_1mhz + 1'b1;
 + end
 + end
 +
 + reg one_wire_buffer;​
 + reg [3:​0] cnt_main;​
 + reg [7:​0] data_wr;​
 + reg [7:​0] data_wr_buffer;​
 + reg [2:​0] cnt_init;​
 + reg [19:​0] cnt_delay;​
 + reg [19:​0] num_delay;​
 + reg [5:​0] cnt_write;​
 + reg [5:​0] cnt_read;​
 + reg [15:​0] temperature;​
 + reg [7:​0] temperature_buffer;​
 + reg [2:0] state = IDLE;
 + reg [2:0] state_back = IDLE;
 + always@(posedge clk_1mhz or negedge rst_n_in) begin
 + if(!rst_n_in) begin
 + state <= IDLE;
 + state_back <= IDLE;
 + cnt_main <= 4'd0;
 + cnt_init <= 3'd0;
 + cnt_write <= 6'd0;
 + cnt_read <= 6'd0;
 + cnt_delay <= 20'd0;
 + one_wire_buffer <= 1'bz;
 + temperature <= 16'h0;
 + end else begin
 + case(state)
 + IDLE:​begin
 + state <= MAIN;
 + state_back <= MAIN;
 + cnt_main <= 4'd0;
 + cnt_init <= 3'd0;
 + cnt_write <= 6'd0;
 + cnt_read <= 6'd0;
 + cnt_delay <= 20'd0;
 + one_wire_buffer <= 1'bz;
 + end
 + MAIN:​begin
 + if(cnt_main >= 4'd11) cnt_main <= 1'b0;
 + else cnt_main <= cnt_main + 1'b1;
 + case(cnt_main)
 + 4'​d0:​ begin state <= INIT; end
 + 4'​d1:​ begin data_wr <= 8'​hcc;​state <= WRITE; end
 + 4'​d2:​ begin data_wr <= 8'​h44;​state <= WRITE; end
 + 4'​d3:​ begin num_delay <= 20'​d750000;​state <= DELAY;​state_back <= MAIN; end
 +
 + 4'​d4:​ begin state <= INIT; end
 + 4'​d5:​ begin data_wr <= 8'​hcc;​state <= WRITE; end
 + 4'​d6:​ begin data_wr <= 8'​hbe;​state <= WRITE; end
 +
 + 4'​d7:​ begin state <= READ; end
 + 4'​d8:​ begin temperature[7:​0] <= temperature_buffer;​ end
 +
 + 4'​d9:​ begin state <= READ; end
 + 4'​d10:​ begin temperature[15:​8] <= temperature_buffer;​ end
 +
 + 4'​d11:​ begin state <= IDLE;​data_out <= temperature;​ end
 + default:​ state <= IDLE;
 + endcase
 + end
 + INIT:​begin
 + if(cnt_init >= 3'd6) cnt_init <= 1'b0;
 + else cnt_init <= cnt_init + 1'b1;
 + case(cnt_init)
 + 3'​d0:​ begin one_wire_buffer <= 1'b0; end
 + 3'​d1:​ begin num_delay <= 20'​d500;​state <= DELAY;​state_back <= INIT; end
 + 3'​d2:​ begin one_wire_buffer <= 1'bz; end
 + 3'​d3:​ begin num_delay <= 20'​d100;​state <= DELAY;​state_back <= INIT; end
 + 3'​d4:​ begin if(one_wire) state <= IDLE; else state <= INIT; end
 + 3'​d5:​ begin num_delay <= 20'​d400;​state <= DELAY;​state_back <= INIT; end
 + 3'​d6:​ begin state <= MAIN; end
 + default:​ state <= IDLE;
 + endcase
 + end
 + WRITE:​begin
 + if(cnt_write >= 6'd50) cnt_write <= 1'b0;
 + else cnt_write <= cnt_write + 1'b1;
 + case(cnt_write)
 + //​lock data_wr
 + 6'​d0:​ begin data_wr_buffer <= data_wr; end
 + //​write bit 0
 + 6'​d1:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d2:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d3:​ begin one_wire_buffer <= data_wr_buffer[0];​ end
 + 6'​d4:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d5:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d6:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​write bit 1
 + 6'​d7:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d8:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d9:​ begin one_wire_buffer <= data_wr_buffer[1];​ end
 + 6'​d10:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d11:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d12:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​write bit 2
 + 6'​d13:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d14:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d15:​ begin one_wire_buffer <= data_wr_buffer[2];​ end
 + 6'​d16:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d17:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d18:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​write bit 3
 + 6'​d19:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d20:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d21:​ begin one_wire_buffer <= data_wr_buffer[3];​ end
 + 6'​d22:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d23:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d24:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​write bit 4
 + 6'​d25:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d26:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d27:​ begin one_wire_buffer <= data_wr_buffer[4];​ end
 + 6'​d28:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d29:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d30:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​write bit 5
 + 6'​d31:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d32:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d33:​ begin one_wire_buffer <= data_wr_buffer[5];​ end
 + 6'​d34:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d35:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d36:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​write bit 6
 + 6'​d37:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d38:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d39:​ begin one_wire_buffer <= data_wr_buffer[6];​ end
 + 6'​d40:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d41:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d42:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​write bit 7
 + 6'​d43:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d44:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d45:​ begin one_wire_buffer <= data_wr_buffer[7];​ end
 + 6'​d46:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d47:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d48:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= WRITE; end
 + //​back to main
 + 6'​d49:​ begin num_delay <= 20'​d80;​state <= DELAY;​state_back <= WRITE; end
 + 6'​d50:​ begin state <= MAIN; end
 + default:​ state <= IDLE;
 + endcase
 + end
 + READ:​begin
 + if(cnt_read >= 6'd48) cnt_read <= 1'b0;
 + else cnt_read <= cnt_read + 1'b1;
 + case(cnt_read)
 + //​read bit 0
 + 6'​d0:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d1:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d2:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d3:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d4:​ begin temperature_buffer[0] <= one_wire; end
 + 6'​d5:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​read bit 1
 + 6'​d6:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d7:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d8:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d9:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d10:​ begin temperature_buffer[1] <= one_wire; end
 + 6'​d11:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​read bit 2
 + 6'​d12:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d13:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d14:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d15:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d16:​ begin temperature_buffer[2] <= one_wire; end
 + 6'​d17:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​read bit 3
 + 6'​d18:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d19:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d20:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d21:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d22:​ begin temperature_buffer[3] <= one_wire; end
 + 6'​d23:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​read bit 4
 + 6'​d24:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d25:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d26:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d27:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d28:​ begin temperature_buffer[4] <= one_wire; end
 + 6'​d29:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​read bit 5
 + 6'​d30:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d31:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d32:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d33:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d34:​ begin temperature_buffer[5] <= one_wire; end
 + 6'​d35:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​read bit 6
 + 6'​d36:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d37:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d38:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d39:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d40:​ begin temperature_buffer[6] <= one_wire; end
 + 6'​d41:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​read bit 7
 + 6'​d42:​ begin one_wire_buffer <= 1'b0; end
 + 6'​d43:​ begin num_delay <= 20'​d2;​state <= DELAY;​state_back <= READ; end
 + 6'​d44:​ begin one_wire_buffer <= 1'bz; end
 + 6'​d45:​ begin num_delay <= 20'​d10;​state <= DELAY;​state_back <= READ; end
 + 6'​d46:​ begin temperature_buffer[7] <= one_wire; end
 + 6'​d47:​ begin num_delay <= 20'​d55;​state <= DELAY;​state_back <= READ; end
 + //​back to main
 + 6'​d48:​ begin state <= MAIN; end
 + default:​ state <= IDLE;
 + endcase
 + end
 + DELAY:​begin
 + if(cnt_delay >= num_delay) begin
 + cnt_delay <= 1'b0;
 + state <= state_back; ​
 + end else cnt_delay <= cnt_delay + 1'b1;
 + end
 + endcase
 + end
 + end
 +
 + assign one_wire = one_wire_buffer;​
 +
 +endmodule
 +</​code>​