STEP FPGA驱动温度传感器DS18B20Z

本节将和大家一起使用FPGA驱动底板上的DS18B20Z单总线温度传感器进行温度数据的采集。

DS18B20是我们日常设计中常用的一款温度传感器芯片，只需要一根总线就可以实现通信，非常的方便，我们的STEP-BaseBoard底板上就集成了温度传感器DS18B20Z，下面我们就一起来学习一下它的硬件链接及驱动方法。
DS18B20Z只有一根总线，硬件电路非常简单，但是一定记得总线需要做上拉处理，如下图总线上连接了10K（上拉电阻取值可以一定范围内自行调整）的上拉电阻，另外我们使用FPGA驱动，一定记得将FPGA对应的管脚同样作上拉配置，重要的事情说三遍，总线上拉，总线上拉，总线上拉。
聊完硬件连接，接下来简要介绍如何驱动（更加详细的信息需要大家参考数据手册），不同的功能需求对应不同寄存器配置，本设计执行的操作案例如下。

下面为大家展示上述案例中每个环节的时序要求：

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Module:Segment_scan 
// 
// Author: Step
// 
// Description: Display with Segment tube
// 
// Web: www.stepfpga.com
// 
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date:   |Changes Made:
// V1.0     |2015/11/11   |Initial ver
// --------------------------------------------------------------------
module Segment_scan
(
input				clk_in,			//系统时钟
input				rst_n_in,		//系统复位，低有效
input		[3:0]	seg_data_1,		//SEG1 数码管要显示的数据
input		[3:0]	seg_data_2,		//SEG2 数码管要显示的数据
input		[3:0]	seg_data_3,		//SEG3 数码管要显示的数据
input		[3:0]	seg_data_4,		//SEG4 数码管要显示的数据
input		[3:0]	seg_data_5,		//SEG5 数码管要显示的数据
input		[3:0]	seg_data_6,		//SEG6 数码管要显示的数据
input		[5:0]	seg_data_en,	//各位数码管数据显示使能，[MSB~LSB]=[SEG6~SEG1]
input		[5:0]	seg_dot_en,		//各位数码管小数点显示使能，[MSB~LSB]=[SEG6~SEG1]
output	reg			rclk_out,		//74HC595的RCK管脚
output	reg			sclk_out,		//74HC595的SCK管脚
output	reg			sdio_out		//74HC595的SER管脚
);
 
parameter CLK_DIV_PERIOD = 600; //分频系数
 
localparam	IDLE	=	3'd0;
localparam	MAIN	=	3'd1;
localparam	WRITE	=	3'd2;
 
localparam	LOW		=	1'b0;
localparam	HIGH	=	1'b1;
 
//创建数码管的字库，字库数据依段码顺序有关
//这里字库数据[MSB~LSB]={DP,G,F,E,D,C,B,A}
reg[7:0] seg [15:0]; 
initial begin
    seg[0]	=	8'h3f;   //  0
    seg[1]	=	8'h06;   //  1
    seg[2]	=	8'h5b;   //  2
    seg[3]	=	8'h4f;   //  3
    seg[4]	=	8'h66;   //  4
    seg[5]	=	8'h6d;   //  5
    seg[6]	=	8'h7d;   //  6
    seg[7]	=	8'h07;   //  7
    seg[8]	=	8'h7f;   //  8
    seg[9]	=	8'h6f;   //  9
	seg[10]	=	8'h77;   //  A
    seg[11]	=	8'h7c;   //  b
    seg[12]	=	8'h39;   //  C
    seg[13]	=	8'h5e;   //  d
    seg[14]	=	8'h79;   //  E
    seg[15]	=	8'h71;   //  F
end 
 
//计数器对系统时钟信号进行计数
reg[9:0] cnt=0;
always@(posedge clk_in or negedge rst_n_in) begin
	if(!rst_n_in) begin
		cnt <= 1'b0;
	end else begin
		if(cnt>=(CLK_DIV_PERIOD-1)) cnt <= 1'b0;
		else cnt <= cnt + 1'b1;
	end
end
 
//根据计数器计数的周期产生分频的脉冲信号
reg clk_div; 
always@(posedge clk_in or negedge rst_n_in) begin
	if(!rst_n_in) begin
		clk_div <= 1'b0;
	end else begin
		if(cnt==(CLK_DIV_PERIOD-1)) clk_div <= 1'b1;
		else clk_div <= 1'b0;
	end
end
 
//使用状态机完成数码管的扫描和74HC595时序的实现
reg		[15:0]		data_reg;
reg		[2:0]		cnt_main;
reg		[5:0]		cnt_write;
reg		[2:0] 		state = IDLE;
always@(posedge clk_in or negedge rst_n_in) begin
	if(!rst_n_in) begin	//复位状态下，各寄存器置初值
		state <= IDLE;
		cnt_main <= 3'd0;
		cnt_write <= 6'd0;
		sdio_out <= 1'b0;
		sclk_out <= LOW;
		rclk_out <= LOW;
	end else begin
		case(state)
			IDLE:begin	//IDLE作为第一个状态，相当于软复位
					state <= MAIN;
					cnt_main <= 3'd0;
					cnt_write <= 6'd0;
					sdio_out <= 1'b0;
					sclk_out <= LOW;
					rclk_out <= LOW;
				end
			MAIN:begin
					if(cnt_main >= 3'd5) cnt_main <= 1'b0;
					else cnt_main <= cnt_main + 1'b1;
					case(cnt_main)
						//对6位数码管逐位扫描
						3'd0:	begin 
									state <= WRITE;	//在配置完发给74HC595的数据同时跳转至WRITE状态，完成串行时序
									data_reg <= {seg[seg_data_1]|(seg_dot_en[0]?8'h80:8'h00),seg_data_en[0]?8'hfe:8'hff};
									//data_reg[15:8]为段选，data_reg[7:0]为位选
									//seg[seg_data_1]  是根据端口的输入获取相应字库数据
									//seg_dot_en[0]?8'h80:8'h00  是根据小数点显示使能信号 控制SEG1数码管的小数点DP段的电平
									//seg_data_en[0]?8'hfe:8'hff  是根据数据显示使能信号 控制SEG1数码管的位选引脚的电平
								end
						3'd1:	begin 
									state <= WRITE;
									data_reg <= {seg[seg_data_2]|(seg_dot_en[1]?8'h80:8'h00),seg_data_en[1]?8'hfd:8'hff}; 
								end
						3'd2:	begin 
									state <= WRITE;
									data_reg <= {seg[seg_data_3]|(seg_dot_en[2]?8'h80:8'h00),seg_data_en[2]?8'hfb:8'hff}; 
								end
						3'd3:	begin 
									state <= WRITE;
									data_reg <= {seg[seg_data_4]|(seg_dot_en[3]?8'h80:8'h00),seg_data_en[3]?8'hf7:8'hff}; 
								end
						3'd4:	begin 
									state <= WRITE;
									data_reg <= {seg[seg_data_5]|(seg_dot_en[4]?8'h80:8'h00),seg_data_en[4]?8'hef:8'hff};
								end
						3'd5:	begin 
									state <= WRITE;
									data_reg <= {seg[seg_data_6]|(seg_dot_en[5]?8'h80:8'h00),seg_data_en[5]?8'hdf:8'hff}; 
								end
						default: state <= IDLE;
					endcase
				end
			WRITE:begin
					if(clk_div) begin	//74HC595的串行时钟有速度要求，需要按照分频后的节拍
						if(cnt_write >= 6'd33) cnt_write <= 1'b0;
						else cnt_write <= cnt_write + 1'b1;
						case(cnt_write)
							//74HC595是串行转并行的芯片，3路输入可产生8路输出，而且可以级联使用
							//74HC595的时序实现，参考74HC595的芯片手册
							6'd0:  begin sclk_out <= LOW; sdio_out <= data_reg[15]; end		//SCK下降沿时SER更新数据
							6'd1:  begin sclk_out <= HIGH; end								//SCK上升沿时SER数据稳定
							6'd2:  begin sclk_out <= LOW; sdio_out <= data_reg[14]; end
							6'd3:  begin sclk_out <= HIGH; end
							6'd4:  begin sclk_out <= LOW; sdio_out <= data_reg[13]; end
							6'd5:  begin sclk_out <= HIGH; end
							6'd6:  begin sclk_out <= LOW; sdio_out <= data_reg[12]; end
							6'd7:  begin sclk_out <= HIGH; end
							6'd8:  begin sclk_out <= LOW; sdio_out <= data_reg[11]; end
							6'd9:  begin sclk_out <= HIGH; end
							6'd10: begin sclk_out <= LOW; sdio_out <= data_reg[10]; end
							6'd11: begin sclk_out <= HIGH; end
							6'd12: begin sclk_out <= LOW; sdio_out <= data_reg[9]; end
							6'd13: begin sclk_out <= HIGH; end
							6'd14: begin sclk_out <= LOW; sdio_out <= data_reg[8]; end
							6'd15: begin sclk_out <= HIGH; end
							6'd16: begin sclk_out <= LOW; sdio_out <= data_reg[7]; end
							6'd17: begin sclk_out <= HIGH; end
							6'd18: begin sclk_out <= LOW; sdio_out <= data_reg[6]; end
							6'd19: begin sclk_out <= HIGH; end
							6'd20: begin sclk_out <= LOW; sdio_out <= data_reg[5]; end
							6'd21: begin sclk_out <= HIGH; end
							6'd22: begin sclk_out <= LOW; sdio_out <= data_reg[4]; end
							6'd23: begin sclk_out <= HIGH; end
							6'd24: begin sclk_out <= LOW; sdio_out <= data_reg[3]; end
							6'd25: begin sclk_out <= HIGH; end
							6'd26: begin sclk_out <= LOW; sdio_out <= data_reg[2]; end
							6'd27: begin sclk_out <= HIGH; end
							6'd28: begin sclk_out <= LOW; sdio_out <= data_reg[1]; end
							6'd29: begin sclk_out <= HIGH; end
							6'd30: begin sclk_out <= LOW; sdio_out <= data_reg[0]; end
							6'd31: begin sclk_out <= HIGH; end
							6'd32: begin rclk_out <= HIGH; end								//当16位数据传送完成后RCK拉高，输出生效
							6'd33: begin rclk_out <= LOW; state <= MAIN; end
							default: state <= IDLE;
						endcase
					end else begin
						sclk_out <= sclk_out;
						sdio_out <= sdio_out;
						rclk_out <= rclk_out;
						cnt_write <= cnt_write;
						state <= state;
					end
				end
			default: state <= IDLE;
		endcase
	end
end
 
endmodule

本节主要为大家讲解了数码管显示的相关原理及软件设计，需要大家掌握的同时自己创建工程，通过整个设计流程，生成FPGA配置文件加载测试。
如果你对Diamond软件的使用不了解，请参考这里：Diamond的使用。

使用STEP-MXO2第二代的数码管扫描程序: 后续会有下载连接 待更新
使用STEP-MAX10的数码管扫描程序: 后续会有下载连接 待更新