Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.8.0.115.3

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jun 09 15:45:04 2017


Command Line:  synthesis -f pianoshield_impl1_lattice.synproj -gui -msgset C:/Users/TEST/Desktop/pianoshield/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is CSBGA132.
The -d option is LCMXO2-4000HC.
Using package CSBGA132.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-4000HC

### Package : CSBGA132

### Speed   : 4

##########################################################

                                                          

Optimization goal = Balanced
Top-level module name = pianoshield_top.
Target frequency = 1.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/TEST/Desktop/pianoshield (searchpath added)
-p C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/TEST/Desktop/pianoshield/impl1 (searchpath added)
-p C:/Users/TEST/Desktop/pianoshield (searchpath added)
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/beeper.v
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/cap1188_i2c.v
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/clk_quarter.v
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/define_reg.v
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/display.v
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/music_box.v
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/pianoshield_top.v
Verilog design file = C:/Users/TEST/Desktop/pianoshield/source/PWM.v
NGD file = pianoshield_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/beeper.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/cap1188_i2c.v. VERI-1482
INFO - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(18): analyzing included file c:/users/test/desktop/pianoshield/source/define_reg.v. VERI-1328
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/clk_quarter.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/define_reg.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/display.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/music_box.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/pianoshield_top.v. VERI-1482
Analyzing Verilog file c:/users/test/desktop/pianoshield/source/pwm.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): pianoshield_top
INFO - synthesis: c:/users/test/desktop/pianoshield/source/pianoshield_top.v(18): compiling module pianoshield_top. VERI-1018
INFO - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(20): compiling module cap1188_i2c. VERI-1018
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(43): net init_reg does not have a driver. VDB-1002
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(44): net init_dat does not have a driver. VDB-1002
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(51): net work_reg does not have a driver. VDB-1002
INFO - synthesis: c:/users/test/desktop/pianoshield/source/beeper.v(18): compiling module beeper. VERI-1018
INFO - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(18): compiling module music_box. VERI-1018
INFO - synthesis: c:/users/test/desktop/pianoshield/source/clk_quarter.v(18): compiling module clk_quarter. VERI-1018
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(121): expression size 8 truncated to fit in target size 5. VERI-1209
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(126): expression size 8 truncated to fit in target size 5. VERI-1209
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(133): expression size 8 truncated to fit in target size 5. VERI-1209
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(139): expression size 8 truncated to fit in target size 5. VERI-1209
INFO - synthesis: c:/users/test/desktop/pianoshield/source/pwm.v(18): compiling module pwm. VERI-1018
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/pwm.v(60): expression size 32 truncated to fit in target size 1. VERI-1209
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(36): net freq does not have a driver. VDB-1002
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(37): net PUA does not have a driver. VDB-1002
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(38): net PUB does not have a driver. VDB-1002
INFO - synthesis: c:/users/test/desktop/pianoshield/source/display.v(18): compiling module display. VERI-1018
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/display.v(27): net seg does not have a driver. VDB-1002
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = pianoshield_top.
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(43): ram init_reg_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(44): ram init_dat_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(51): ram work_reg_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(36): ram freq_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(37): ram PUA_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/music_box.v(38): ram PUB_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/display.v(27): ram seg_original_ramnet has no write-port on it. VDB-1038
INFO - synthesis: Extracted state machine for register '\musicbox_u/state' with one-hot encoding
State machine has 3 reachable states with original encodings of:

 00 

 01 

 10 

original encoding -> new encoding (one-hot encoding)

 00 -> 001

 01 -> 010

 10 -> 100




WARNING - synthesis: Bit 0 of Register \musicbox_u/state_FSM is stuck at Zero
WARNING - synthesis: Bit 0 of Register \musicbox_u/pucounter_max is stuck at One
WARNING - synthesis: Bit 1 of Register \musicbox_u/pucounter_max is stuck at Zero
WARNING - synthesis: Bit 2 of Register \musicbox_u/pucounter_max is stuck at Zero
WARNING - synthesis: Bit 3 of Register \musicbox_u/pucounter_max is stuck at Zero
WARNING - synthesis: Bit 5 of Register \musicbox_u/pucounter_max is stuck at Zero
WARNING - synthesis: Bit 6 of Register \musicbox_u/pucounter_max is stuck at Zero
WARNING - synthesis: Bit 7 of Register \musicbox_u/pucounter_max is stuck at Zero
WARNING - synthesis: Bit 0 of Register \musicbox_u/freq_index is stuck at Zero
WARNING - synthesis: c:/users/test/desktop/pianoshield/source/cap1188_i2c.v(302): Register \cap1188_i2c_u/state_back_i0_i3 is stuck at Zero. VDB-5013
GSR instance connected to net rst_n_in_c.
Duplicate register/latch removal. \cap1188_i2c_u/data_wr_i0_i7 is a one-to-one match with \cap1188_i2c_u/data_wr_i0_i3.
Duplicate register/latch removal. \cap1188_i2c_u/data_wr_i0_i6 is a one-to-one match with \cap1188_i2c_u/data_wr_i0_i4.
Duplicate register/latch removal. \cap1188_i2c_u/work_num_i0_i3 is a one-to-one match with \cap1188_i2c_u/work_num_i0_i2.
Duplicate register/latch removal. \cap1188_i2c_u/work_num_i0_i1 is a one-to-one match with \cap1188_i2c_u/work_num_i0_i3.
Applying 1.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in pianoshield_top_drc.log.
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file pianoshield_impl1.ngd.

################### Begin Area Report (pianoshield_top)######################
Number of register bits => 215 of 4635 (4 % )
BB => 1
CCU2D => 108
FD1P3AX => 61
FD1P3AY => 3
FD1P3IX => 13
FD1P3JX => 5
FD1S3AX => 14
FD1S3AY => 24
FD1S3IX => 94
FD1S3JX => 1
GSR => 1
IB => 2
L6MUX21 => 2
LUT4 => 463
OB => 28
PDPW8KC => 1
PFUMX => 35
ROM256X1A => 10
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 3
  Net : clk_in_c, loads : 205
  Net : cap1188_i2c_u/clk_200khz, loads : 15
  Net : musicbox_u/clk_inst/clk_4Hz, loads : 8
Clock Enable Nets
Number of Clock Enables: 41
Top 10 highest fanout Clock Enables:
  Net : cap1188_i2c_u/clk_in_c_enable_59, loads : 9
  Net : cap1188_i2c_u/clk_in_c_enable_41, loads : 8
  Net : cap1188_i2c_u/clk_in_c_enable_30, loads : 8
  Net : rst_n_in_c, loads : 6
  Net : cap1188_i2c_u/clk_in_c_enable_60, loads : 5
  Net : musicbox_u/state_1_N_389_0, loads : 4
  Net : cap1188_i2c_u/clk_in_c_enable_11, loads : 3
  Net : cap1188_i2c_u/clk_in_c_enable_74, loads : 2
  Net : cap1188_i2c_u/clk_in_c_enable_15, loads : 2
  Net : cap1188_i2c_u/sda_out_N_285, loads : 2
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : cap1188_i2c_u/state_0, loads : 62
  Net : cap1188_i2c_u/state_1, loads : 56
  Net : cap1188_i2c_u/state_2, loads : 48
  Net : rst_n_in_c, loads : 34
  Net : musicbox_u/clk_inst/counter_31__N_511, loads : 33
  Net : musicbox_u/speaker_N_412_31, loads : 32
  Net : musicbox_u/speaker_I_0/n6768, loads : 32
  Net : cap1188_i2c_u/state_3, loads : 29
  Net : cap1188_i2c_u/cnt_work_3, loads : 25
  Net : tone_3, loads : 22
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk2 [get_nets \musicbox_u/clk_4Hz]     |    1.000 MHz|  135.612 MHz|     4  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets clk_200khz]              |            -|            -|     0  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets clk_in_c]                |    1.000 MHz|   79.064 MHz|     7  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 75.539  MB

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Elapsed CPU time for LSE flow : 3.666  secs
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