Setting log file to 'C:/Users/TEST/Desktop/pianoshield/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/beeper.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/cap1188_i2c.v
INFO - C:/Users/TEST/Desktop/pianoshield/source/cap1188_i2c.v(18,10-18,24) (VERI-1328) analyzing included file C:/Users/TEST/Desktop/pianoshield/source/define_reg.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/clk_quarter.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/define_reg.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/display.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/music_box.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/pianoshield_top.v
(VERI-1482) Analyzing Verilog file C:/Users/TEST/Desktop/pianoshield/source/PWM.v
INFO - C:/Users/TEST/Desktop/pianoshield/source/pianoshield_top.v(18,8-18,23) (VERI-1018) compiling module pianoshield_top
INFO - C:/Users/TEST/Desktop/pianoshield/source/pianoshield_top.v(18,1-141,10) (VERI-9000) elaborating module 'pianoshield_top'
INFO - C:/Users/TEST/Desktop/pianoshield/source/cap1188_i2c.v(20,1-308,10) (VERI-9000) elaborating module 'cap1188_i2c_uniq_1'
INFO - C:/Users/TEST/Desktop/pianoshield/source/beeper.v(18,1-90,10) (VERI-9000) elaborating module 'beeper_uniq_1'
INFO - C:/Users/TEST/Desktop/pianoshield/source/music_box.v(18,1-179,10) (VERI-9000) elaborating module 'music_box_uniq_1'
INFO - C:/Users/TEST/Desktop/pianoshield/source/display.v(18,1-79,10) (VERI-9000) elaborating module 'display_uniq_1'
INFO - C:/Users/TEST/Desktop/pianoshield/source/clk_quarter.v(18,1-43,10) (VERI-9000) elaborating module 'clk_quarter_uniq_1'
INFO - C:/Users/TEST/Desktop/pianoshield/source/PWM.v(18,1-62,10) (VERI-9000) elaborating module 'pwm_uniq_1'
Done: design load finished with (0) errors, and (0) warnings