Setting log file to 'C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file E:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/clk_div.v
(VERI-1482) Analyzing Verilog file C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master.v
(VERI-1482) Analyzing Verilog file C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master_config.v
(VERI-1482) Analyzing Verilog file C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master_logic.v
INFO - C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master.v(2,8-2,18) (VERI-1018) compiling module i2c_master
INFO - C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master.v(2,1-48,10) (VERI-9000) elaborating module 'i2c_master'
INFO - C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/clk_div.v(18,1-78,10) (VERI-9000) elaborating module 'clk_div_uniq_1'
INFO - C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master_config.v(1,1-108,10) (VERI-9000) elaborating module 'i2c_master_config_uniq_1'
INFO - C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master_logic.v(1,1-689,10) (VERI-9000) elaborating module 'i2c_master_logic_uniq_1'
Done: design load finished with (0) errors, and (0) warnings