Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.8.0.115.3

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Sat Dec 16 18:05:12 2017


Command Line:  synthesis -f i2c_master_AT24C02_i2c_master_AT24C02_lattice.synproj -gui 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is CSBGA132.
The -d option is LCMXO2-4000HC.
Using package CSBGA132.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-4000HC

### Package : CSBGA132

### Speed   : 4

##########################################################

                                                          

Optimization goal = Balanced
Top-level module name = i2c_master.
Target frequency = 1.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/22822/Desktop/i2c_master_AT24C02 (searchpath added)
-p E:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02 (searchpath added)
-p C:/Users/22822/Desktop/i2c_master_AT24C02 (searchpath added)
Verilog design file = C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/clk_div.v
Verilog design file = C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master.v
Verilog design file = C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master_config.v
Verilog design file = C:/Users/22822/Desktop/i2c_master_AT24C02/i2c_master_AT24C02/source/i2c_master_logic.v
NGD file = i2c_master_AT24C02_i2c_master_AT24C02.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file E:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/clk_div.v. VERI-1482
Analyzing Verilog file c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/i2c_master.v. VERI-1482
Analyzing Verilog file c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/i2c_master_config.v. VERI-1482
Analyzing Verilog file c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/i2c_master_logic.v. VERI-1482
Analyzing Verilog file E:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): i2c_master
INFO - synthesis: c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/i2c_master.v(2): compiling module i2c_master. VERI-1018
INFO - synthesis: c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/clk_div.v(18): compiling module clk_div. VERI-1018
INFO - synthesis: c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/i2c_master_config.v(1): compiling module i2c_master_config. VERI-1018
INFO - synthesis: c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/i2c_master_logic.v(1): compiling module i2c_master_logic. VERI-1018
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c4000.nph' in environment: E:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = i2c_master.
INFO - synthesis: Extracted state machine for register '\i2c_master_config_inst/i2c_state' with one-hot encoding
State machine has 4 reachable states with original encodings of:

 00 

 01 

 10 

 11 

original encoding -> new encoding (one-hot encoding)

 00 -> 0001

 01 -> 0010

 10 -> 0100

 11 -> 1000




WARNING - synthesis: Bit 0 of Register \i2c_master_config_inst/i2c_config is stuck at Zero
WARNING - synthesis: Bit 1 of Register \i2c_master_config_inst/i2c_config is stuck at Zero
WARNING - synthesis: Bit 2 of Register \i2c_master_config_inst/i2c_config is stuck at Zero
WARNING - synthesis: Bit 3 of Register \i2c_master_config_inst/i2c_config is stuck at Zero
WARNING - synthesis: Bit 4 of Register \i2c_master_config_inst/i2c_config is stuck at Zero
WARNING - synthesis: Bit 6 of Register \i2c_master_config_inst/i2c_config is stuck at Zero
WARNING - synthesis: Bit 1 of Register \i2c_master_config_inst/i2c_reg_data is stuck at Zero
WARNING - synthesis: Bit 5 of Register \i2c_master_config_inst/i2c_reg_data is stuck at Zero
WARNING - synthesis: Bit 0 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 1 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 2 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 3 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 4 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 5 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 6 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 7 of Register \i2c_master_config_inst/i2c_reg_addr is stuck at Zero
WARNING - synthesis: Bit 1 of Register \i2c_master_config_inst/i2c_dev_addr is stuck at Zero
WARNING - synthesis: Bit 3 of Register \i2c_master_config_inst/i2c_dev_addr is stuck at Zero
WARNING - synthesis: Bit 4 of Register \i2c_master_config_inst/i2c_dev_addr is stuck at Zero
WARNING - synthesis: Bit 5 of Register \i2c_master_config_inst/i2c_dev_addr is stuck at Zero
WARNING - synthesis: Bit 6 of Register \i2c_master_config_inst/i2c_dev_addr is stuck at Zero
WARNING - synthesis: Bit 0 of Register \i2c_master_config_inst/i2c_master_logic_inst/state_current is stuck at Zero
WARNING - synthesis: c:/users/22822/desktop/i2c_master_at24c02/i2c_master_at24c02/source/i2c_master_config.v(70): Register \i2c_master_config_inst/i2c_state_FSM_i3 is stuck at Zero. VDB-5013
GSR instance connected to net rst_n_c.
WARNING - synthesis: Initial value found on instance \i2c_master_config_inst/i2c_master_logic_inst/sda_ctl_511 will be ignored.
Applying 1.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in i2c_master_drc.log.
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'E:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file i2c_master_AT24C02_i2c_master_AT24C02.ngd.

################### Begin Area Report (i2c_master)######################
Number of register bits => 122 of 4635 (2 % )
BB => 1
CCU2D => 32
FD1P3AX => 18
FD1P3AY => 3
FD1P3IX => 47
FD1S3AX => 7
FD1S3AY => 1
FD1S3IX => 46
GSR => 1
IB => 2
LUT4 => 401
OB => 9
PFUMX => 19
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 3
  Net : clk_div_inst/clk_div_100k, loads : 75
  Net : sys_clk_12m_c, loads : 45
  Net : i2c_master_config_inst/i2c_flag, loads : 3
Clock Enable Nets
Number of Clock Enables: 27
Top 10 highest fanout Clock Enables:
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_55, loads : 10
  Net : i2c_master_config_inst/sys_clk_12m_c_enable_8, loads : 8
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_44, loads : 4
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_17, loads : 4
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_54, loads : 4
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_34, loads : 4
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_18, loads : 4
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_27, loads : 4
  Net : i2c_master_config_inst/sys_clk_12m_c_enable_10, loads : 3
  Net : i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_56, loads : 3
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_0, loads : 45
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_3, loads : 42
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_4, loads : 35
  Net : clk_div_inst/n4871, loads : 32
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_13, loads : 29
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_8, loads : 27
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_10, loads : 26
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_5, loads : 25
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_12, loads : 25
  Net : i2c_master_config_inst/i2c_master_logic_inst/state_current_11, loads : 25
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk2 [get_nets clk_div_100k]            |    1.000 MHz|   57.597 MHz|    11  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets                          |             |             |
\i2c_master_config_inst/i2c_flag]       |    1.000 MHz|  291.036 MHz|     2  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets sys_clk_12m_c]           |    1.000 MHz|   98.164 MHz|     6  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 69.891  MB

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Elapsed CPU time for LSE flow : 3.297  secs
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