Lattice Mapping Report File for Design Module 'i2c_master'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-4000HC -t CSBGA132 -s 4 -oc Commercial
     i2c_master_i2c_master.ngd -o i2c_master_i2c_master_map.ncd -pr
     i2c_master_i2c_master.prf -mp i2c_master_i2c_master.mrp -lpf C:/Users/22822
     /Desktop/2/source/i2c_master_PCF8591_ADC/i2c_master/i2c_master_i2c_master.l
     pf -lpf
     C:/Users/22822/Desktop/2/source/i2c_master_PCF8591_ADC/i2c_master.lpf -c 0
     -gui -msgset
     C:/Users/22822/Desktop/2/source/i2c_master_PCF8591_ADC/promote.xml 
Target Vendor:  LATTICE
Target Device:  LCMXO2-4000HCCSBGA132
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.8.0.115.3
Mapped on:  12/18/17  08:37:10


Design Summary
   Number of registers:     89 out of  4635 (2%)
      PFU registers:           89 out of  4320 (2%)
      PIO registers:            0 out of   315 (0%)
   Number of SLICEs:       155 out of  2160 (7%)
      SLICEs as Logic/ROM:    155 out of  2160 (7%)
      SLICEs as RAM:            0 out of  1620 (0%)
      SLICEs as Carry:         32 out of  2160 (1%)
   Number of LUT4s:        309 out of  4320 (7%)
      Number used as logic LUTs:        245
      Number used as distributed RAM:     0
      Number used as ripple logic:       64
      Number used as shift registers:     0
   Number of PIO sites used: 12 + 4(JTAG) out of 105 (15%)
   Number of block RAMs:  0 out of 10 (0%)
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 2 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  2

     Net sys_clk_12m_c: 19 loads, 19 rising, 0 falling (Driver: PIO sys_clk_12m
     )
     Net clk_div_100k: 41 loads, 41 rising, 0 falling (Driver:
     clk_div_inst/clk_p_29 )
   Number of Clock Enables:  13
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_18: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_25: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_35: 3
     loads, 3 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_29: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_7: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_34: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_36: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_22: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_37: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_14: 1
     loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_24: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_20: 2
     loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_40: 2
     loads, 2 LSLICEs
   Number of LSRs:  22
     Net clk_div_inst/n4591: 17 loads, 17 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n6556: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4618: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n6171: 3 loads, 3 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7339: 4 loads, 4 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n6981: 1 loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4632: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7340: 1 loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n6553: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4612: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7816: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7347: 1 loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7811: 1 loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4611: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4616: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4610: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4625: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n4621: 2 loads, 2 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7411: 1 loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7410: 1 loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n7344: 1 loads, 1 LSLICEs
     Net i2c_master_config_inst/i2c_master_logic_inst/n6998: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:

     Net i2c_master_config_inst/i2c_master_logic_inst/state_current_0: 35 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/state_current_2: 25 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/n7838: 23 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/state_current_9: 22 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/n7844: 21 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/state_current_1: 18 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/state_current_4: 18 loads
     Net clk_div_inst/n4591: 17 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/state_current_8: 17 loads
     Net i2c_master_config_inst/i2c_master_logic_inst/state_current_7: 16 loads




   Number of warnings:  0
   Number of errors:    0
     




Design Errors/Warnings

   No errors or warnings present.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| i2c_ack[4]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| rst_n               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| sys_clk_12m         | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| i2c_ack[0]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| i2c_ack[1]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| i2c_ack[2]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| i2c_ack[3]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| i2c_ack[5]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| i2c_ack[6]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| i2c_ack[7]          | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| scl                 | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| sda                 | BIDIR     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+





Removed logic

Signal n3606 was merged into signal
     i2c_master_config_inst/i2c_master_logic_inst/sda_ctl
Signal VCC_net undriven or does not drive anything - clipped.
Signal clk_div_inst/add_4614_2/S1 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/add_4614_2/S0 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/add_4614_2/CI undriven or does not drive anything - clipped.
     
Signal clk_div_inst/add_4614_4/S1 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/add_4614_4/S0 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/add_4614_6/S1 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/add_4614_6/S0 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/cnt_p_1103_add_4_33/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/cnt_p_1103_add_4_33/CO undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_12/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_12/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_18/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_18/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_10/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_10/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_22/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_22/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_24/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_24/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_26/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_26/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_28/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_28/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_30/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_30/CO undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_14/S1 undriven or does not drive anything -
     clipped.

Signal clk_div_inst/add_4614_14/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_20/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_20/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_8/S1 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/add_4614_8/S0 undriven or does not drive anything - clipped.
     
Signal clk_div_inst/cnt_p_1103_add_4_1/S0 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/cnt_p_1103_add_4_1/CI undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_16/S1 undriven or does not drive anything -
     clipped.
Signal clk_div_inst/add_4614_16/S0 undriven or does not drive anything -
     clipped.
Block i2c_master_config_inst/i2c_master_logic_inst/i1430_1_lut was optimized
     away.
Block i5 was optimized away.



Memory Usage


     



GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is 'rst_n_c'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------

     These components have the GSR property set to ENABLED and the local reset
     is synchronous. The components will respond to the synchronous local reset
     and to the unrelated asynchronous reset signal 'rst_n_c' via the GSR
     component.

     Type and number of components of the type: 
   Register = 84 

     Type and instance name of component: 
   Register : clk_div_inst/cnt_p_1103__i0
   Register : clk_div_inst/cnt_p_1103__i31

   Register : clk_div_inst/cnt_p_1103__i30
   Register : clk_div_inst/cnt_p_1103__i29
   Register : clk_div_inst/cnt_p_1103__i28
   Register : clk_div_inst/cnt_p_1103__i27
   Register : clk_div_inst/cnt_p_1103__i26
   Register : clk_div_inst/cnt_p_1103__i25
   Register : clk_div_inst/cnt_p_1103__i24
   Register : clk_div_inst/cnt_p_1103__i23
   Register : clk_div_inst/cnt_p_1103__i22
   Register : clk_div_inst/cnt_p_1103__i21
   Register : clk_div_inst/cnt_p_1103__i20
   Register : clk_div_inst/cnt_p_1103__i19
   Register : clk_div_inst/cnt_p_1103__i18
   Register : clk_div_inst/cnt_p_1103__i17
   Register : clk_div_inst/cnt_p_1103__i16
   Register : clk_div_inst/cnt_p_1103__i15
   Register : clk_div_inst/cnt_p_1103__i14
   Register : clk_div_inst/cnt_p_1103__i13
   Register : clk_div_inst/cnt_p_1103__i12
   Register : clk_div_inst/cnt_p_1103__i11
   Register : clk_div_inst/cnt_p_1103__i10
   Register : clk_div_inst/cnt_p_1103__i9
   Register : clk_div_inst/cnt_p_1103__i8
   Register : clk_div_inst/cnt_p_1103__i7
   Register : clk_div_inst/cnt_p_1103__i6
   Register : clk_div_inst/cnt_p_1103__i5
   Register : clk_div_inst/cnt_p_1103__i4
   Register : clk_div_inst/cnt_p_1103__i3
   Register : clk_div_inst/cnt_p_1103__i2
   Register : clk_div_inst/cnt_p_1103__i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_r_i0_i0
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_read_reg_data_1108__i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1104__i3
        
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i13
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i11
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i10
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i8
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_i0_i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_stop_i0_i2
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_read_reg_data_1108__i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_i0_i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i3
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_i0_i0
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_stop_i0_i0
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i4
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i5
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i9
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_s_ack_i0_i0
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_read_reg_data_1108__i3
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_r_addr_i0_i0

   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_r_i0_i0
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_r_i0_i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_r_i0_i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i14
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_r_i0_i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_r_i0_i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_s_ack_i0_i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/i2c_ack__i5
   Register : i2c_master_config_inst/i2c_master_logic_inst/i2c_ack__i4
   Register : i2c_master_config_inst/i2c_master_logic_inst/i2c_ack__i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_s_ack_i0_i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_r_addr_i0_i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/i2c_ack__i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_r_addr_i0_i2
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_read_reg_data_1108__i0
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_r_1107__i0
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1105__i0
        
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_i0_i2
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_i0_i0
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1104__i0
        
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1104__i1
        
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1105__i1
        
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1105__i2
        
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_stop_i0_i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1104__i2
        
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_i0_i1
   Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1105__i3
        
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_r_1107__i1
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_r_1107__i2
   Register :
        i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_r_1107__i3



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 51 MB
        









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     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights
     reserved.