Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sat Dec 16 18:05:16 2017 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: i2c_master Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 1000.000000 -name clk2 [get_nets clk_div_100k] 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 982.638ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 (from clk_div_100k +) Destination: FD1S3AX D \i2c_master_config_inst/i2c_master_logic_inst/state_current_i1 (to clk_div_100k +) Delay: 17.202ns (29.7% logic, 70.3% route), 11 logic levels. Constraint Details: 17.202ns data_path \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 to \i2c_master_config_inst/i2c_master_logic_inst/state_current_i1 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 982.638ns Path Details: \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 to \i2c_master_config_inst/i2c_master_logic_inst/state_current_i1 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 (from clk_div_100k) Route 35 e 2.102 \i2c_master_config_inst/i2c_master_logic_inst/state_current[4] LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_adj_47 Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n280 LUT4 --- 0.493 D to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_3_lut_4_lut_adj_96 Route 2 e 1.141 \i2c_master_config_inst/i2c_master_logic_inst/n310 LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_2_lut_3_lut_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_55 Route 9 e 1.574 \i2c_master_config_inst/i2c_master_logic_inst/n6755 LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_3_lut_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n4 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_4_lut_adj_58 Route 5 e 1.405 \i2c_master_config_inst/i2c_master_logic_inst/n1854 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_rep_86 Route 2 e 1.141 \i2c_master_config_inst/i2c_master_logic_inst/n10235 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i4273_4_lut Route 1 e 0.020 \i2c_master_config_inst/i2c_master_logic_inst/n2929 MUXL5 --- 0.233 BLUT to Z \i2c_master_config_inst/i2c_master_logic_inst/mux_1192_Mux_0_i1 Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n3428 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1675_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/state_next[0] -------- 17.202 (29.7% logic, 70.3% route), 11 logic levels. Passed: The following path meets requirements by 982.838ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 (from clk_div_100k +) Destination: FD1S3AX D \i2c_master_config_inst/i2c_master_logic_inst/state_current_i3 (to clk_div_100k +) Delay: 17.002ns (30.1% logic, 69.9% route), 11 logic levels. Constraint Details: 17.002ns data_path \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 to \i2c_master_config_inst/i2c_master_logic_inst/state_current_i3 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 982.838ns Path Details: \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 to \i2c_master_config_inst/i2c_master_logic_inst/state_current_i3 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_master_logic_inst/state_current_i5 (from clk_div_100k) Route 35 e 2.102 \i2c_master_config_inst/i2c_master_logic_inst/state_current[4] LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_adj_47 Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n280 LUT4 --- 0.493 D to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_3_lut_4_lut_adj_96 Route 2 e 1.141 \i2c_master_config_inst/i2c_master_logic_inst/n310 LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_2_lut_3_lut_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_55 Route 9 e 1.574 \i2c_master_config_inst/i2c_master_logic_inst/n6755 LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_3_lut_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n4 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_4_lut_adj_58 Route 5 e 1.405 \i2c_master_config_inst/i2c_master_logic_inst/n1854 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_rep_84_3_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n10233 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i4298_4_lut Route 1 e 0.020 \i2c_master_config_inst/i2c_master_logic_inst/n2927 MUXL5 --- 0.233 BLUT to Z \i2c_master_config_inst/i2c_master_logic_inst/mux_1192_Mux_2_i1 Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n3426 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1708_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/state_next[2] -------- 17.002 (30.1% logic, 69.9% route), 11 logic levels. Passed: The following path meets requirements by 982.846ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \i2c_master_config_inst/i2c_master_logic_inst/state_current_i10 (from clk_div_100k +) Destination: FD1S3AX D \i2c_master_config_inst/i2c_master_logic_inst/state_current_i1 (to clk_div_100k +) Delay: 16.994ns (30.1% logic, 69.9% route), 11 logic levels. Constraint Details: 16.994ns data_path \i2c_master_config_inst/i2c_master_logic_inst/state_current_i10 to \i2c_master_config_inst/i2c_master_logic_inst/state_current_i1 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 982.846ns Path Details: \i2c_master_config_inst/i2c_master_logic_inst/state_current_i10 to \i2c_master_config_inst/i2c_master_logic_inst/state_current_i1 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_master_logic_inst/state_current_i10 (from clk_div_100k) Route 23 e 1.894 \i2c_master_config_inst/i2c_master_logic_inst/state_current[9] LUT4 --- 0.493 A to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_adj_47 Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n280 LUT4 --- 0.493 D to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_3_lut_4_lut_adj_96 Route 2 e 1.141 \i2c_master_config_inst/i2c_master_logic_inst/n310 LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_2_lut_3_lut_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n6 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i3_4_lut_adj_55 Route 9 e 1.574 \i2c_master_config_inst/i2c_master_logic_inst/n6755 LUT4 --- 0.493 C to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_3_lut_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n4 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i2_4_lut_adj_58 Route 5 e 1.405 \i2c_master_config_inst/i2c_master_logic_inst/n1854 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1_2_lut_rep_86 Route 2 e 1.141 \i2c_master_config_inst/i2c_master_logic_inst/n10235 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i4273_4_lut Route 1 e 0.020 \i2c_master_config_inst/i2c_master_logic_inst/n2929 MUXL5 --- 0.233 BLUT to Z \i2c_master_config_inst/i2c_master_logic_inst/mux_1192_Mux_0_i1 Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/n3428 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i2c_master_logic_inst/i1675_4_lut Route 1 e 0.941 \i2c_master_config_inst/i2c_master_logic_inst/state_next[0] -------- 16.994 (30.1% logic, 69.9% route), 11 logic levels. Report: 17.362 ns is the maximum delay for this constraint. ================================================================================ Constraint: create_clock -period 1000.000000 -name clk1 [get_nets \i2c_master_config_inst/i2c_flag] 4 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 996.564ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \i2c_master_config_inst/i2c_state_FSM_i1 (from \i2c_master_config_inst/i2c_flag +) Destination: FD1S3AX D \i2c_master_config_inst/i2c_state_FSM_i2 (to \i2c_master_config_inst/i2c_flag +) Delay: 3.276ns (28.6% logic, 71.4% route), 2 logic levels. Constraint Details: 3.276ns data_path \i2c_master_config_inst/i2c_state_FSM_i1 to \i2c_master_config_inst/i2c_state_FSM_i2 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 996.564ns Path Details: \i2c_master_config_inst/i2c_state_FSM_i1 to \i2c_master_config_inst/i2c_state_FSM_i2 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_state_FSM_i1 (from \i2c_master_config_inst/i2c_flag) Route 4 e 1.398 \i2c_master_config_inst/i2c_config_7__N_105[2] LUT4 --- 0.493 A to Z \i2c_master_config_inst/i4233_2_lut Route 1 e 0.941 \i2c_master_config_inst/n94 -------- 3.276 (28.6% logic, 71.4% route), 2 logic levels. Passed: The following path meets requirements by 996.647ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK \i2c_master_config_inst/i2c_state_FSM_i2 (from \i2c_master_config_inst/i2c_flag +) Destination: FD1S3AX D \i2c_master_config_inst/i2c_state_FSM_i2 (to \i2c_master_config_inst/i2c_flag +) Delay: 3.193ns (29.3% logic, 70.7% route), 2 logic levels. Constraint Details: 3.193ns data_path \i2c_master_config_inst/i2c_state_FSM_i2 to \i2c_master_config_inst/i2c_state_FSM_i2 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 996.647ns Path Details: \i2c_master_config_inst/i2c_state_FSM_i2 to \i2c_master_config_inst/i2c_state_FSM_i2 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_state_FSM_i2 (from \i2c_master_config_inst/i2c_flag) Route 3 e 1.315 \i2c_master_config_inst/i2c_state_1__N_115 LUT4 --- 0.493 B to Z \i2c_master_config_inst/i4233_2_lut Route 1 e 0.941 \i2c_master_config_inst/n94 -------- 3.193 (29.3% logic, 70.7% route), 2 logic levels. Passed: The following path meets requirements by 998.081ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AY CK \i2c_master_config_inst/i2c_state_FSM_i0 (from \i2c_master_config_inst/i2c_flag +) Destination: FD1S3IX D \i2c_master_config_inst/i2c_state_FSM_i1 (to \i2c_master_config_inst/i2c_flag +) Delay: 1.759ns (25.2% logic, 74.8% route), 1 logic levels. Constraint Details: 1.759ns data_path \i2c_master_config_inst/i2c_state_FSM_i0 to \i2c_master_config_inst/i2c_state_FSM_i1 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 998.081ns Path Details: \i2c_master_config_inst/i2c_state_FSM_i0 to \i2c_master_config_inst/i2c_state_FSM_i1 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \i2c_master_config_inst/i2c_state_FSM_i0 (from \i2c_master_config_inst/i2c_flag) Route 3 e 1.315 \i2c_master_config_inst/sys_clk_12m_c_enable_10 -------- 1.759 (25.2% logic, 74.8% route), 1 logic levels. Report: 3.436 ns is the maximum delay for this constraint. ================================================================================ Constraint: create_clock -period 1000.000000 -name clk0 [get_nets sys_clk_12m_c] 1597 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 989.813ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \clk_div_inst/cnt_p_1193__i26 (from sys_clk_12m_c +) Destination: FD1S3IX CD \clk_div_inst/cnt_p_1193__i0 (to sys_clk_12m_c +) Delay: 10.027ns (29.0% logic, 71.0% route), 6 logic levels. Constraint Details: 10.027ns data_path \clk_div_inst/cnt_p_1193__i26 to \clk_div_inst/cnt_p_1193__i0 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 989.813ns Path Details: \clk_div_inst/cnt_p_1193__i26 to \clk_div_inst/cnt_p_1193__i0 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \clk_div_inst/cnt_p_1193__i26 (from sys_clk_12m_c) Route 3 e 1.315 \clk_div_inst/cnt_p[26] LUT4 --- 0.493 B to Z \clk_div_inst/i8_2_lut Route 1 e 0.941 \clk_div_inst/n34 LUT4 --- 0.493 C to Z \clk_div_inst/i22_4_lut Route 1 e 0.941 \clk_div_inst/n48 LUT4 --- 0.493 B to Z \clk_div_inst/i24_4_lut Route 1 e 0.941 \clk_div_inst/n50 LUT4 --- 0.493 B to Z \clk_div_inst/i25_4_lut Route 1 e 0.941 \clk_div_inst/n9073 LUT4 --- 0.493 A to Z \clk_div_inst/i7422_4_lut Route 32 e 2.039 \clk_div_inst/n4871 -------- 10.027 (29.0% logic, 71.0% route), 6 logic levels. Passed: The following path meets requirements by 989.813ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \clk_div_inst/cnt_p_1193__i26 (from sys_clk_12m_c +) Destination: FD1S3IX CD \clk_div_inst/cnt_p_1193__i31 (to sys_clk_12m_c +) Delay: 10.027ns (29.0% logic, 71.0% route), 6 logic levels. Constraint Details: 10.027ns data_path \clk_div_inst/cnt_p_1193__i26 to \clk_div_inst/cnt_p_1193__i31 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 989.813ns Path Details: \clk_div_inst/cnt_p_1193__i26 to \clk_div_inst/cnt_p_1193__i31 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \clk_div_inst/cnt_p_1193__i26 (from sys_clk_12m_c) Route 3 e 1.315 \clk_div_inst/cnt_p[26] LUT4 --- 0.493 B to Z \clk_div_inst/i8_2_lut Route 1 e 0.941 \clk_div_inst/n34 LUT4 --- 0.493 C to Z \clk_div_inst/i22_4_lut Route 1 e 0.941 \clk_div_inst/n48 LUT4 --- 0.493 B to Z \clk_div_inst/i24_4_lut Route 1 e 0.941 \clk_div_inst/n50 LUT4 --- 0.493 B to Z \clk_div_inst/i25_4_lut Route 1 e 0.941 \clk_div_inst/n9073 LUT4 --- 0.493 A to Z \clk_div_inst/i7422_4_lut Route 32 e 2.039 \clk_div_inst/n4871 -------- 10.027 (29.0% logic, 71.0% route), 6 logic levels. Passed: The following path meets requirements by 989.813ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \clk_div_inst/cnt_p_1193__i26 (from sys_clk_12m_c +) Destination: FD1S3IX CD \clk_div_inst/cnt_p_1193__i30 (to sys_clk_12m_c +) Delay: 10.027ns (29.0% logic, 71.0% route), 6 logic levels. Constraint Details: 10.027ns data_path \clk_div_inst/cnt_p_1193__i26 to \clk_div_inst/cnt_p_1193__i30 meets 1000.000ns delay constraint less 0.160ns L_S requirement (totaling 999.840ns) by 989.813ns Path Details: \clk_div_inst/cnt_p_1193__i26 to \clk_div_inst/cnt_p_1193__i30 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \clk_div_inst/cnt_p_1193__i26 (from sys_clk_12m_c) Route 3 e 1.315 \clk_div_inst/cnt_p[26] LUT4 --- 0.493 B to Z \clk_div_inst/i8_2_lut Route 1 e 0.941 \clk_div_inst/n34 LUT4 --- 0.493 C to Z \clk_div_inst/i22_4_lut Route 1 e 0.941 \clk_div_inst/n48 LUT4 --- 0.493 B to Z \clk_div_inst/i24_4_lut Route 1 e 0.941 \clk_div_inst/n50 LUT4 --- 0.493 B to Z \clk_div_inst/i25_4_lut Route 1 e 0.941 \clk_div_inst/n9073 LUT4 --- 0.493 A to Z \clk_div_inst/i7422_4_lut Route 32 e 2.039 \clk_div_inst/n4871 -------- 10.027 (29.0% logic, 71.0% route), 6 logic levels. Report: 10.187 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk2 [get_nets clk_div_100k] | 1000.000 ns| 17.362 ns| 11 | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets | | | \i2c_master_config_inst/i2c_flag] | 1000.000 ns| 3.436 ns| 2 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets sys_clk_12m_c] | 1000.000 ns| 10.187 ns| 6 | | | -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 7637 paths, 577 nets, and 1814 connections (94.7% coverage) Peak memory: 73072640 bytes, TRCE: 1847296 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs