PAR: Place And Route Diamond (64-bit) 3.8.0.115.3. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Sat Dec 16 18:09:41 2017 E:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f i2c_master_AT24C02_i2c_master_AT24C02.p2t i2c_master_AT24C02_i2c_master_AT24C02_map.ncd i2c_master_AT24C02_i2c_master_AT24C02.dir i2c_master_AT24C02_i2c_master_AT24C02.prf -gui Preference file: i2c_master_AT24C02_i2c_master_AT24C02.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 - - - - 06 Complete * : Design saved. Total (real) run time for 1-seed: 6 secs par done! Lattice Place and Route Report for Design "i2c_master_AT24C02_i2c_master_AT24C02_map.ncd" Sat Dec 16 18:09:41 2017 Best Par Run PAR: Place And Route Diamond (64-bit) 3.8.0.115.3. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF i2c_master_AT24C02_i2c_master_AT24C02_map.ncd i2c_master_AT24C02_i2c_master_AT24C02.dir/5_1.ncd i2c_master_AT24C02_i2c_master_AT24C02.prf Preference file: i2c_master_AT24C02_i2c_master_AT24C02.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file i2c_master_AT24C02_i2c_master_AT24C02_map.ncd. Design name: i2c_master NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 4 Loading device for application par from file 'xo2c4000.nph' in environment: E:/lscc/diamond/3.8_x64/ispfpga. Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 12+4(JTAG)/280 6% used 12+4(JTAG)/105 15% bonded SLICE 233/2160 10% used GSR 1/1 100% used Number of Signals: 567 Number of Connections: 1779 Pin Constraint Summary: 12 out of 12 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: clk_div_100k (driver: clk_div_inst/SLICE_28, clk load #: 55) sys_clk_12m_c (driver: sys_clk_12m, clk load #: 26) WARNING - par: Signal "sys_clk_12m_c" is selected to use Primary clock resources. However, its driver comp "sys_clk_12m" is located at "C1", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. The following 1 signal is selected to use the secondary clock routing resources: clk_div_inst/n4871 (driver: clk_div_inst/SLICE_117, clk load #: 0, sr load #: 17, ce load #: 0) Signal rst_n_c is selected as Global Set/Reset. Starting Placer Phase 0. ........... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. ..................... Placer score = 86380. Finished Placer Phase 1. REAL time: 3 secs Starting Placer Phase 2. . Placer score = 85384 Finished Placer Phase 2. REAL time: 3 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 280 (0%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "clk_div_100k" from Q1 on comp "clk_div_inst/SLICE_28" on site "R3C16C", clk load = 55 PRIMARY "sys_clk_12m_c" from comp "sys_clk_12m" on PIO site "C1 (PL4A)", clk load = 26 SECONDARY "clk_div_inst/n4871" from F0 on comp "clk_div_inst/SLICE_117" on site "R12C15C", clk load = 0, ce load = 0, sr load = 17 PRIMARY : 2 out of 8 (25%) SECONDARY: 1 out of 8 (12%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 12 + 4(JTAG) out of 280 (5.7%) PIO sites used. 12 + 4(JTAG) out of 105 (15.2%) bonded PIO sites used. Number of PIO comps: 12; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+---------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+---------------+------------+-----------+ | 0 | 2 / 26 ( 7%) | 2.5V | - | | 1 | 3 / 26 ( 11%) | 2.5V | - | | 2 | 6 / 28 ( 21%) | 2.5V | - | | 3 | 0 / 7 ( 0%) | - | - | | 4 | 0 / 8 ( 0%) | - | - | | 5 | 1 / 10 ( 10%) | 2.5V | - | +----------+---------------+------------+-----------+ Total placer CPU time: 2 secs Dumping design to file i2c_master_AT24C02_i2c_master_AT24C02.dir/5_1.ncd. ----------------------------------------------------------------- INFO - par: ASE feature is off due to non timing-driven settings. ----------------------------------------------------------------- 0 connections routed; 1779 unrouted. Starting router resource preassignment WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=i2c_master_config_inst/i2c_flag loads=3 clock_loads=3 Completed router resource preassignment. Real time: 5 secs Start NBR router at 18:09:46 12/16/17 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 18:09:46 12/16/17 Start NBR section for initial routing at 18:09:46 12/16/17 Level 4, iteration 1 33(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 18:09:46 12/16/17 Level 4, iteration 1 9(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Level 4, iteration 2 5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Level 4, iteration 3 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Level 4, iteration 4 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Start NBR section for re-routing at 18:09:46 12/16/17 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 5 secs Start NBR section for post-routing at 18:09:46 12/16/17 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : <n/a> Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=i2c_master_config_inst/i2c_flag loads=3 clock_loads=3 Total CPU time 4 secs Total REAL time: 5 secs Completely routed. End of route. 1779 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file i2c_master_AT24C02_i2c_master_AT24C02.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a> PAR_SUMMARY::Timing score<setup/<ns>> = <n/a> PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a> PAR_SUMMARY::Timing score<hold /<ns>> = <n/a> PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 5 secs Total REAL time to completion: 6 secs par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.