###System controller

\\

####项目
[[https://opencores.org/projects/ac97|AC 97 Controller IP Core]]\\
[[https://opencores.org/projects/ahbmaster|AHBmaster for FPGA of microsemi]]\\
[[https://opencores.org/projects/wbc_parallel_master|External parallel port to internal wishbone master interface]]\\
[[https://opencores.org/projects/mem_ctrl|Memory Controller IP Core]]\\
[[https://opencores.org/projects/ata|OCIDEC (OpenCores IDE Controller)]]\\
[[https://opencores.org/projects/pci|PCI bridge]]\\
[[https://opencores.org/projects/pcie_vera_tb|PCI Express x1 16bit VERA testbench]]\\
[[https://opencores.org/projects/pci_to_wb|PCI slave to WB master]]\\
[[https://opencores.org/projects/pci32tlite_oc|PCI Target]]\\

\\

[[https://opencores.org/projects/pcie_sg_dma|PCIe SG DMA controller]]\\
[[https://opencores.org/projects/pcie_ds_dma|PCIe_DS_DMA]]\\
[[https://opencores.org/projects/pcie_mini|PCIe_mini (PCI-Express to Wishbone Bridge for Xilinx FPGAs)]]\\
[[https://opencores.org/projects/pcie_mini_axi4s_wb|PCIe_mini_axi4s_wb]]\\
[[https://opencores.org/projects/pci_mini|pci_mini]]\\
[[https://opencores.org/projects/powersupplysequencer|Power Supply Sequencer]]\\
[[https://opencores.org/projects/pic|Programmable Interrupt Controller]]\\
[[https://opencores.org/projects/rs232_syscon|RS232 system controller]]\\
[[https://opencores.org/projects/scsi_chip|scsi_chip]]\\
[[https://opencores.org/projects/sdram|Synchronous-DRAM Controller]]\\
[[https://opencores.org/projects/dualspartainc6713cpci|TI DSP and Xilinx FPGA Dev Board]]\\
[[https://opencores.org/projects/wb_lcd|WB LCD Character Display Controller]]\\

\\

[[https://opencores.org/projects/virtex7_pcie_dma|Wupper: PCIe DMA Engine for Xilinx FPGAs]]\\