###Communication controller ####项目 [[https://opencores.org/projects/10_100m_ethernet-fifo_convertor|10/100M Ethernet-FIFO convertor]]\\ [[https://opencores.org/projects/mac_layer_switch|100 MB/s Ethernet MAC Layer Switch]]\\ [[https://opencores.org/projects/1000base-x|1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)]]\\ [[https://opencores.org/projects/ethmac10g|10G Ethernet MAC]]\\ [[https://opencores.org/projects/ethernet_tri_mode|10_100_1000 Mbps tri-mode ethernet MAC]]\\ [[https://opencores.org/projects/16_qam_qadm|16 Quadrature Amplitude Modulator and Demodulator]]\\ [[https://opencores.org/projects/udp_ip_stack|1G eth UDP / IP Stack]]\\ [[https://opencores.org/projects/ether_arp_1g|1G Ethernet ARP]]\\ [[https://opencores.org/projects/1g_ethernet_dpi|1G Ethernet DPI]]\\ [[https://opencores.org/projects/8b10b_encdec|8b10b Encoder/Decoder]]\\ [[https://opencores.org/projects/a_vhd_16550_uart|a VHDL 16550 UART core]]\\ [[https://opencores.org/projects/a_vhdl_can_controller|A VHDL CAN Protocol Controller]]\\ [[https://opencores.org/projects/adat_optical_feed_forward_receiver|adat receiver]]\\ [[https://opencores.org/projects/ahci_sata|ahci]]\\ [[https://opencores.org/projects/line_codes|AMI / HDB1 Line Codes]]\\ [[https://opencores.org/projects/spi_master_controller|Another SPI Controller (with FIFO)]]\\ [[https://opencores.org/projects/wbuart32|Another Wishbone Controlled UART]]\\ [[https://opencores.org/projects/apbi2c|APB to I2C]]\\ [[https://opencores.org/projects/apb2spi|APB to SPI]]\\ [[https://opencores.org/projects/a429_transmitter_receiver|ARINC 429 Transmitter and Receiver]]\\ [[https://opencores.org/projects/async_8b10b_encoder_decoder|Async 8b/10b enc/dec]]\\ [[https://opencores.org/projects/asynchronous_master_spi|Asynchronous SPI master]]\\ [[https://opencores.org/projects/auto_baud|Automatic BAUD rate generator]]\\ [[https://opencores.org/projects/baudgen|baud generator]]\\ [[https://opencores.org/projects/bit_gpio|Bitwise addressable GPIO]]\\ [[https://opencores.org/projects/bluespec-80211atransmitter|Bluespec 802.11a Transmitter]]\\ [[https://opencores.org/projects/bluetooth|Bluetooth baseband controller]]\\ [[https://opencores.org/projects/can|CAN Protocol Controller]]\\ [[https://opencores.org/projects/cheap_ethernet|Cheap Ethernet interface]]\\ [[https://opencores.org/projects/core1990_interlaken|Core1990: Interlaken protocol]]\\ [[https://opencores.org/projects/dmt_tx|DMT Transceiver]]\\ [[https://opencores.org/projects/dmx512|DMX512 transceiver]]\\ [[https://opencores.org/projects/osdvu|Documented Verilog UART]]\\ [[https://opencores.org/projects/dqpskmap|DQPSK Mapper]]\\ [[https://opencores.org/projects/e1framerdeframer|E1 Framer/Deframer]]\\ [[https://opencores.org/projects/e1framer|E1-G.703,G.704,G.706 framer/deframer]]\\ [[https://opencores.org/projects/i2s|EBU/spdif to I2S project]]\\ [[https://opencores.org/projects/epp|EPP v1.9]]\\ [[https://opencores.org/projects/etherblade_net_ver1|Etherblade.net - FPGA ethernet line-rate encapsulator (EoIP, EoMPLS, PBB etc)]]\\ [[http://example.comhttps://opencores.org/projects/gbiteth|Ethernet 100/1000 Mbps]]\\ [[https://opencores.org/projects/xge_ll_mac|Ethernet 10GE Low Latency MAC]]\\ \\ [[https://opencores.org/projects/xge_mac|Ethernet 10GE MAC]]\\ \\ [[https://opencores.org/projects/ethmac|Ethernet MAC 10/100 Mbps]]\\ [[https://opencores.org/projects/smii|Ethernet SMII]]\\ [[https://opencores.org/projects/esoc|Ethernet Switch on Configurable Logic]]\\ [[https://opencores.org/projects/ezusb_io|EZUSB communication core]]\\ [[https://opencores.org/projects/fade_ether_protocol|Fade - Light L3 Ethernet protocol for transmission of data from FPGA to embedded PC]]\\ [[https://opencores.org/projects/firewire|FireWire (IEEE 1394)]]\\ [[https://opencores.org/projects/fpga-cf|FPGA Communication Framework]]\\ [[https://opencores.org/projects/uart_fpga_slow_control|FPGA remote slow control via UART 16550]]\\ [[https://opencores.org/projects/ft2232hcore|FT2232H USB Avalon Core]]\\ [[https://opencores.org/projects/ft245r_interface|FT245R interface]]\\ [[https://opencores.org/projects/ftdi_wb_bridge|FTDI Async FIFO I/F to Wishbone Bridge]]\\ [[https://opencores.org/projects/ft60x_axi|FTDI FT60x USB3.0 to AXI bus master]]\\ [[https://opencores.org/projects/gamepads|Gamepads]]\\ [[https://opencores.org/projects/gpio|General-Purpose I/O (GPIO) Core]]\\ [[https://opencores.org/projects/gpib_controller|GPIB (IEEE-488) controller]]\\ [[https://opencores.org/projects/ha1588|Hardware Assisted IEEE 1588 IP Core]]\\ [[https://opencores.org/projects/hdbn|HDB3/B3ZS Encoder+Decoder]]\\ [[https://opencores.org/projects/hdlc|HDLC controller]]\\ [[https://opencores.org/projects/ht_tunnel|HyperTransport Tunnel]]\\ \\ [[https://opencores.org/projects/i2c|I2C controller core]]\\ [[https://opencores.org/projects/i2c_master_slave|I2C Master Slave Core]]\\ [[https://opencores.org/projects/i2c_master_slave_core|I2C master/slave Core]]\\ [[https://opencores.org/projects/iicmb|I2C Multiple Bus Controller]]\\ [[https://opencores.org/projects/i2crepeater|I2C Repeater]]\\ [[https://opencores.org/projects/i2cslave|I2C Slave]]\\ [[https://opencores.org/projects/i2clog|I2C Traffic Logger]]\\ [[https://opencores.org/projects/i2cgpio|i2cgpio]]\\ [[https://opencores.org/projects/i2c_to_wb|i2c_to_wb]]\\ [[https://opencores.org/projects/i2s_interface|I2S Interface]]\\ [[https://opencores.org/projects/i2sparalell|I2S to Paralell ADC/DAC controller]]\\ [[https://opencores.org/projects/i2s_to_parallel|I2S to Parallel Interface]]\\ [[https://opencores.org/projects/i2s_to_wb|I2S to WishBone]]\\ [[https://opencores.org/projects/i8255|i8255 realisation in Verilog]]\\ [[https://opencores.org/projects/802154phycore|IEEE 802.15.4 Core (physical layer)]]\\ [[https://opencores.org/projects/crc802154|IEEE 802.15.4 CRC]]\\ [[https://opencores.org/projects/ipv4_packet_transmitter|IPv4 Ethernet Packet Creator and Transmitter]]\\ [[https://opencores.org/projects/irda|IrDA]]\\ [[https://opencores.org/projects/iso7816_3_master|Iso7816_3_Master]]\\ [[https://opencores.org/projects/jtag_master|JTAG Master]]\\ [[https://opencores.org/projects/jtag_slave|JTAG Slave / BoundaryScan Slave]]\\ [[https://opencores.org/projects/usb_dongle_fpga|LPC ROM emulator on USB dongle FPGA core set]]\\ [[https://opencores.org/projects/openlzs|lzs]]\\ [[https://opencores.org/projects/madi_receiver|MADI Receiver]]\\ [[https://opencores.org/projects/manchesterwireless|Manchester Decoder for Wireless]]\\ [[https://opencores.org/projects/man2uart|Manchester to UART converter]]\\ [[https://opencores.org/projects/manchesteruart|Manchester UART]]\\ [[https://opencores.org/projects/minimac|Minimac - the minimalist Ethernet MAC]]\\ [[https://opencores.org/projects/muart|Minimal UART Core]]\\ [[https://opencores.org/projects/multimicrophone_interface|Multimicrophone Interface]]\\ [[https://opencores.org/projects/nec_ir_decoder|nec ir remote control decoder]]\\ [[https://opencores.org/projects/neopixel_fpga|neopixel ws2812]]\\ [[https://opencores.org/projects/ofdm|OFDM modem]]\\ [[https://opencores.org/projects/softusb|OHCI Full/Low-Speed USB Host Controller]]\\ [[https://opencores.org/projects/onewire|One Wire Master]]\\ [[https://opencores.org/projects/op2p|OP2P (OpenPeerToPeer Interface)]]\\ [[https://opencores.org/projects/spi_slave|OPB SPI Slave]]\\ [[https://opencores.org/projects/opb_onewire|OPB-compatible OneWire Master]]\\ [[https://opencores.org/projects/opb_usblite|opb_usblite]]\\ [[https://opencores.org/projects/pc_fpga_com|PC-FPGA Communication Platform]]\\ [[https://opencores.org/projects/wb2axip|Pipelined wishbone to AXI converter]]\\ [[https://opencores.org/projects/cxd9731|Playstation 2 network adaptor IC CXD9731]]\\ [[https://opencores.org/projects/plb2wbbridge|PLB-to-WB Bridge]]\\ [[https://opencores.org/projects/ps2_host_controller|PS/2 Host Controller]]\\ [[https://opencores.org/projects/ps2core|PS2 Core]]\\ [[https://opencores.org/projects/qspiflash|Quad SPI Flash Controller]]\\ [[https://opencores.org/projects/quadraturecount|Quadrature Decoder / Counter]]\\ [[https://opencores.org/projects/rio|RapidIO IP library]]\\ [[https://opencores.org/projects/rs232_interface|RS232]]\\ [[https://opencores.org/projects/rs232_with_buffer_and_wb|RS232]]\\ [[https://opencores.org/projects/rtfsimpleuart|rtfSimpleUart]]\\ [[https://opencores.org/projects/rxaui_interface_and_xaui_to_rxaui_interface_adapter|RXAUI Interface and XAUI to RXAUI Interface Adapter]]\\ [[https://opencores.org/projects/sata2_host_controller|SATA 2 HOST Controller]]\\ [[https://opencores.org/projects/nysa_sata|SATA Controller]]\\ [[https://opencores.org/projects/sata_phy|SATA PHY]]\\ [[https://opencores.org/projects/saturn|Saturn]]\\ [[https://opencores.org/projects/scan_based_serial_communication|Scan Based Serial Communication]]\\ \\ [[https://opencores.org/projects/sdcard_mass_storage_controller|sd card controller]]\\ [[https://opencores.org/projects/sd_mmc_emulator|SD/eMMC/MMC card emulator]]\\ [[https://opencores.org/projects/spi_boot|SD/MMC Bootloader]]\\ [[https://opencores.org/projects/spimaster|SD/MMC Controller]]\\ [[https://opencores.org/projects/sdhc-sc-core|SDHC Self Configuring Core]]\\ [[https://opencores.org/projects/sdram_axi4|SDRAM AXI4]]\\ [[https://opencores.org/projects/sata_controller_core|Serial ATA Host Bus Adapter Core for Virtex 6]]\\ [[https://opencores.org/projects/sertopar|Serial to parallel converter]]\\ [[https://opencores.org/projects/uart|Serial UART]]\\ [[https://opencores.org/projects/miniuart2|Serial Uart]]\\ [[https://opencores.org/projects/parallel_io_through_fiber|Serializer / Deserializer for audio fiber optic]]\\ [[https://opencores.org/projects/sgmii|SGMII]]\\ [[https://opencores.org/projects/aes3rx|Simple AES3 / SPDIF receiver]]\\ [[https://opencores.org/projects/sasc|Simple Asynchronous Serial Controller]]\\ [[https://opencores.org/projects/mmuart|Simple RS232 UART]]\\ [[https://opencores.org/projects/simple_uart_for_fpga|https://opencores.org/projects/mmuart]]\\ [[https://opencores.org/projects/ss_pcm|Single Slot PCM Interface]]\\ \\ [[https://opencores.org/projects/sockit_owm|Small 1-wire (onewire) master, with Altera tools integration]]\\ [[https://opencores.org/projects/iso7816-3|Smartcard interface (ISO7816-3)]]\\ [[https://opencores.org/projects/smbus_if|smbus_if]]\\ [[https://opencores.org/projects/spacewire|SpaceWire]]\\ [[https://opencores.org/projects/spacewire_light|SpaceWire Light]]\\ [[https://opencores.org/projects/spacewiresystemc|SpaceWireSystemC]]\\ [[https://opencores.org/projects/spdif_interface|SPDIF Interface]]\\ [[https://opencores.org/projects/spdif_transmitter|SPDIF Transmitter]]\\ [[https://opencores.org/projects/sdspi|SPI based SD card controller]]\\ [[https://opencores.org/projects/spi|SPI controller core]]\\ [[https://opencores.org/projects/spi_core_dsp_s3ean_kits|SPI Controller for AD/DA chips on S3E/A/AN Starter Kits]]\\ [[https://opencores.org/projects/simple_spi|SPI core]]\\ [[https://opencores.org/projects/spiflashcontroller|SPI Flash controller]]\\ [[https://opencores.org/projects/spi_master_lightweight|SPI Master Lightweight]]\\ [[https://opencores.org/projects/spiadc|spi master receiver for ADC (AD747x)]]\\ [[https://opencores.org/projects/spi_master_slave|SPI Master/Slave Interface]]\\ [[https://opencores.org/projects/spidac|SPI serial DAC interface]]\\ [[https://opencores.org/projects/spi_verilog_master_slave|SPI Verilog Master & Slave modules]]\\ [[https://opencores.org/projects/spi_slave_wb_master|SPI-slave Wishbone-Master]]\\ [[https://opencores.org/projects/spigpio|spigpio]]\\ [[https://opencores.org/projects/spislave|spislave]]\\ [[https://opencores.org/projects/spicxif|SPIxIF]]\\ [[https://opencores.org/projects/sport|SPORT Interface]]\\ [[https://opencores.org/projects/ssp_slv|SSP_Slv]]\\ [[https://opencores.org/projects/ssp_uart|SSP_UART]]\\ [[https://opencores.org/projects/steppermotordrive|Stepper Motor Controller]]\\ [[https://opencores.org/projects/sio|Super-I/O (SIO) controller]]\\ [[https://opencores.org/projects/usb11|SystemC USB1.1 IP Core]]\\ [[https://opencores.org/projects/systemverilog-uart16550|SystemVerilog uart16550]]\\ [[https://opencores.org/projects/tcp_ip_core_w_dhcp|TCP IP Core]]\\ [[https://opencores.org/projects/tcp_socket|TCP/IP socket]]\\ [[https://opencores.org/projects/tdm|TDM controller]]\\ [[https://opencores.org/projects/aic1106_avalon_ip|TI TLV320AIC1106 PCM Codec Altera Avalon IP core]]\\ [[https://opencores.org/projects/tdm_switch|TIME SLOT INTERCHANGE DIGITAL SWITCH]]\\ [[https://opencores.org/projects/tiny_spi|tiny SPI]]\\ [[https://opencores.org/projects/uart_fifo_cpu_if_sv_testbench|Uart (FIFO cpu interface) with SV Self-Checking Testbench]]\\ [[https://opencores.org/projects/uart16550|UART 16550 core]]\\ [[https://opencores.org/projects/uart_block|Uart block]]\\ [[https://opencores.org/projects/uart_fiber|UART to / from fiber optic]]\\ \\ [[https://opencores.org/projects/uart2bus|UART to Bus]]\\ [[https://opencores.org/projects/uart2spi|UART To SPI]]\\ [[https://opencores.org/projects/uart_plb|ART with PLB interface]]\\ [[https://opencores.org/projects/uart16750|UART16750]]\\ [[https://opencores.org/projects/uart6551|uart6551]]\\ [[https://opencores.org/projects/uart8systemc|UART8SYSTEMC]]\\ [[https://opencores.org/projects/udp_ip__core|UDP/IP Core]]\\ [[https://opencores.org/projects/udp_ipv4_for_10g_ethernet|UDP/IPv4 for 10G Ethernet]]\\ [[https://opencores.org/projects/ulpi_wrapper|ULPI Wrapper]]\\ [[https://opencores.org/projects/usb11_phy_translation|USB 1.1 PHY (VHDL)]]\\ [[https://opencores.org/projects/usb11_sim_model|USB 1.1 Simulation (VHDL)]]\\ [[https://opencores.org/projects/usb1_funct|USB 1.1 Function IP Core]]\\ [[https://opencores.org/projects/usbhostslave|USB 1.1 Host and Function IP core]]\\ [[https://opencores.org/projects/usb_phy|USB 1.1 PHY]]\\ [[https://opencores.org/projects/usb|USB 2.0 Function Core]]\\ [[https://opencores.org/projects/usb_device_core|USB Device Core]]\\ [[https://opencores.org/projects/usb_ft232h_avalon-mm_interface|USB FT232H Avalon-MM interface]\\ [[https://opencores.org/projects/usb_host_core|USB Host Core]]\\ [[https://opencores.org/projects/usb2uart|USB to UART]]\\ [[https://opencores.org/projects/versatile_io|Versatile IO]]\\ [[https://opencores.org/projects/vspi|vSPI]]\\ [[https://opencores.org/projects/wb_uart|wb_uart]]\\ [[https://opencores.org/projects/wiegand_ctl|Wiegand Controller (SIA AC-01-1996.10)]]\\ [[https://opencores.org/projects/wb_lpc|Wishbone LPC Host and Peripheral Bridge]]\\ [[https://opencores.org/projects/wb2axi4|Wishbone protocol to axi4 protocol]]\\ [[https://opencores.org/projects/wrimm|Wishbone Register Bank Intercon Multi-master Multi-slave]]\\ [[https://opencores.org/projects/sd_card_controller|Wishbone SD Card Controller]]\\ [[https://opencores.org/projects/wishbone_uart_controller|wishbone uart controller 8 bit]]\\ [[https://opencores.org/projects/wishboneaxi|WishboneAXI]]\\ [[https://opencores.org/projects/xspi|xSPi]]\\ [[https://opencores.org/projects/yanu|YANU - UART with predictive interrupt events on Rx/Tx buffers state]]\\