### ADC采样的Verilog逻辑设计
从8位并行ADC获取数据，并将数据存储在RAM中。

<code verilog>

// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Module: ADC_Sample
// 
// Author: Step
// 
// Description: ADC_Sample
// 
// Web: www.stepfpga.com
//
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date:   |Changes Made:
// V1.1     |2016/10/30   |Initial ver
// --------------------------------------------------------------------
module ADC_Sample
(
	input		clk_in, // system clock
	input		rst_n_in, //system reset, active low
	
//	input		[3:0]	sample_jump,
	input		adc_done,
	input		[7:0]	adc_data,
	
	input		[7:0]	trig_data,
	input		sample_en,
	output	reg	sample_done,
	
	output	reg	ram_adc_clk_en,
	output	reg	[7:0]	ram_adc_addr,
	output	reg	[7:0]	ram_adc_data	
);
	
	reg [7:0] adc_data_r;
	always@(posedge clk_in or negedge rst_n_in) begin
		if(!rst_n_in) begin
			adc_data_r <= 1'b0;
		end else if(adc_done) begin
			adc_data_r <= adc_data;
		end else begin
			adc_data_r <= adc_data_r;
		end
	end	
	
	reg[15:0] cnt_trig;
	reg       trig_en;
	always@(posedge clk_in or negedge rst_n_in) begin
		if(!rst_n_in) begin
			cnt_trig <= 1'b0;
			trig_en <= 1'b0;
		end else begin
			if(sample_en && (!trig_en)) begin
				if(adc_done) begin
					if(((adc_data_r <= trig_data)&&(adc_data >= trig_data))||(cnt_trig >= 16'd60000)) begin trig_en <= 1'b1; cnt_trig <= 1'b0; end 
					else begin cnt_trig <= cnt_trig + 1'b1; trig_en <= 1'b0; end 
				end else begin
					cnt_trig <= cnt_trig;
					trig_en <= trig_en;
				end
			end else if(sample_done) begin
				cnt_trig <= 1'b0;
				trig_en <= 1'b0;
			end else begin 
				cnt_trig <= cnt_trig;
				trig_en <= trig_en;
			end
		end
	end	
	
	reg	[7:0] 	cnt;
	always@(negedge clk_in or negedge rst_n_in) begin
		if(!rst_n_in) begin
			cnt <= 8'd0;
			sample_done <= 1'b0;
		end else begin
			if(sample_en) begin
				if(adc_done && trig_en) begin
					if(cnt >= 8'd240) begin
						cnt <= 1'b0;
						sample_done <= 1'b1;
					end else begin
						cnt <= cnt + 1'b1;
						sample_done <= 1'b0;
						ram_adc_clk_en <= 1'b1;
						ram_adc_addr <= cnt;
						ram_adc_data <= (adc_data>>1);//8'd240-(adc_data>>1);
					end
				end
			end else begin
				sample_done <= 1'b0;
				ram_adc_clk_en <= 1'b0;
				ram_adc_addr <= 8'd0;
				ram_adc_data <= 8'b0;
			end
		end
	end
	
endmodule

</code>