* Up/Down Counter (State Machine) - KiCad simulation demo (up-down-counter), CC BY-SA 4.0, (c) KiCad developers
* https://gitlab.com/kicad/code/kicad/-/tree/master/demos/simulation/up-down-counter
* Netlist exported with kicad-cli 9; model files from the project are inlined below.
* Some vendor models use PSpice syntax: run ngspice in compatibility mode (put 'set ngbehavior=psa'
* in .spiceinit), as KiCad's simulator does.
.title KiCad schematic
* ---- begin state-machine-3b-count.lib ----
* another state machine example
* by Holger Vogt, July 9th, 2020
* 3-bit counter in a subcircuit with 5 V analog in and out

*** counter
.subckt 3bcounter clock updown out_b0 out_b1 out_b2
* Define a simple 3 bit up/down counter that counts clk edges.
* Digital outputs are on b2 b1 b0.
*   inputs  clock   reset     outputs (all digital)
a0  [upd]  clk    n_zero   [b2 b1 b0]   state2

* This needs to be edited: enter the absolute path of file state-3bit-count.in
.model state2 d_state(state_file = "state-3bit-count.in")
*.model state2 d_state(state_file = "state-3bit-count.in")

* Digital "one" and "zero"
a1 n_one pullup1
.model pullup1 d_pullup(load = 1pF)
a2 n_zero pulldown1
.model pulldown1 d_pulldown(load = 1pF)

* Convert the digital outputs to analog
a3 [b2] [out_b2] dac1
a4 [b1] [out_b1] dac1
a5 [b0] [out_b0] dac1
.model dac1 dac_bridge(out_low = 0 out_high = 5 out_undef = 2.5)
* Convert the analog inputs to digital
a6 [clock] [clk] adc1
a7 [updown] [upd] adc1
.model adc1 adc_bridge(in_low = 0.3 in_high = 3.5)
.ends
*** end counter
* ---- end state-machine-3b-count.lib ----
Vclk1 /clk GND PULSE( 0 5 1u 1u 1u 10u 24u ) 
Vupd1 /ud GND PULSE( 0 5 1u 1u 1u 500u 1m ) 
XU1 /clk /ud /q1 /q2 /q3 3bcounter
* analysis from the project's simulator workbook (up-down-c.wbk)
.tran 1u 2m
.save all
.end