基于小脚丫FPGA的综合技能训练平台

项目目标：

利用ADC制作一个数字电压表

项目要求：

1、旋转电位计可以产生0-3.3V的电压

2、利用板上的串行ADC对电压进行转换

3、将电压值在板上的OLED屏幕上显示出来

项目器件：

包含基于Lattice的STEP-XO2 FPGA的核心模块

项目软件：

Lattice Diamond

项目实现思路：

项目系统整体由两个模块组成：数模转换模块和显示屏驱动模块。分别用于获取电压数值以及在屏幕上的显示。示意图如下：

项目原理图：

项目分析：

由实现思路和原理图可知，我们可以通过ADC的芯片ADS7868对旋转电位计的模拟量进行采集，将采集到的二进制电压信号转化为BCD码，然后实时地显示在两个数码管和OLED屏幕上，以基本完成项目的要求。

项目代码：

为了方便代码的编写与理解，我将本次项目的完整代码分为了5个部分。

第一部分是pll部分。由查阅资料可知，ADC芯片的频率在3.4MHz时其采样率达到最优，因此，此处运用IP核以满足频率分频以保证其采样率。

/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
/* Module Version: 5.7 */
/* D:\Diamond\Diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang verilog -synth lse -arch xo2c00 -type pll -fin 12 -fclkop 120 -fclkop_tol 0.0 -fclkos 6 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phase_cntl STATIC -fb_mode 1 */
/* Wed Sep 08 18:55:05 2021 */


`timescale 1 ns / 1 ps
module pll (CLKI, CLKOP, CLKOS)/* synthesis NGD_DRC_MASK=1 */;
input wire CLKI;
output wire CLKOP;
output wire CLKOS;

wire LOCK;
wire CLKOS_t;
wire CLKOP_t;
wire scuba_vlo;

VLO scuba_vlo_inst (.Z(scuba_vlo));

defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
defparam PLLInst_0.MRST_ENA = "DISABLED" ;
defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
defparam PLLInst_0.CLKOS_FPHASE = 0 ;
defparam PLLInst_0.CLKOS_CPHASE = 79 ;
defparam PLLInst_0.CLKOP_FPHASE = 0 ;
defparam PLLInst_0.CLKOP_CPHASE = 3 ;
defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ;
defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
defparam PLLInst_0.FRACN_DIV = 0 ;
defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
 defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
defparam PLLInst_0.CLKOS3_DIV = 1 ;
defparam PLLInst_0.CLKOS2_DIV = 1 ;
defparam PLLInst_0.CLKOS_DIV = 80 ;
defparam PLLInst_0.CLKOP_DIV = 4 ;
defparam PLLInst_0.CLKFB_DIV = 10 ;
defparam PLLInst_0.CLKI_DIV = 1 ;
defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
.RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
.ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
.ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
.PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(),
.CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(),
.PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
/* synthesis FREQUENCY_PIN_CLKOS="6.000000" */
/* synthesis FREQUENCY_PIN_CLKOP="120.000000" */

/* synthesis FREQUENCY_PIN_CLKI="12.000000" */
/* synthesis ICP_CURRENT="7" */
/* synthesis LPF_RESISTOR="8" */;

assign CLKOS = CLKOS_t;
assign CLKOP = CLKOP_t;


// exemplar begin
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 6.000000
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 120.000000
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 12.000000
// exemplar attribute PLLInst_0 ICP_CURRENT 7
// exemplar attribute PLLInst_0 LPF_RESISTOR 8
// exemplar end

endmodule

第二部分ADC部分是用核心板驱动ADC芯片来采集电压数据，从而满足项目的第一点要求。

module ADC
(
input CLKIOS_c, //系统时钟
input rst_n, //系统复位，低有效
output reg adc_cs, //SPI总线CS
output reg adc_clk, //SPI总线SCK
input adc_dat, //SPI总线SDA
output reg adc_done, //ADC采样完成标志
output reg [7:0] adc_data //ADC采样数据
);
reg [7:0] cnt; //计数器
always @(posedge CLKIOS_c or negedge rst_n)
if(!rst_n) cnt <= 1'b0;
else if(cnt >= 8'd24) cnt <= 1'b0;
else cnt <= cnt + 1'b1;

always @(posedge CLKIOS_c or negedge rst_n)
if(!rst_n) begin
adc_cs <= 1; adc_clk <= 1;
end
else case(cnt)
8'd0 : begin adc_cs <= 1; adc_clk <= 1; end
8'd1 : begin adc_cs <= 0; adc_clk <= 1; end
8'd2,8'd4,8'd6,8'd8,8'd10,8'd12,
8'd14,8'd16,8'd18,8'd20,8'd22,8'd24:
begin adc_cs <= 0; adc_clk <= 0; end
8'd3 : begin adc_cs <= 0; adc_clk <= 1; end //0
8'd5 : begin adc_cs <= 0; adc_clk <= 1; end //1
8'd7 : begin adc_cs <= 0; adc_clk <= 1; end //2
8'd9 : begin adc_cs <= 0; adc_clk <= 1; adc_data[7] <= adc_dat; end //3
8'd11 : begin adc_cs <= 0; adc_clk <= 1; adc_data[6] <= adc_dat; end //4
8'd13 : begin adc_cs <= 0; adc_clk <= 1; adc_data[5] <= adc_dat; end //5
8'd15 : begin adc_cs <= 0; adc_clk <= 1; adc_data[4] <= adc_dat; end //6
8'd17 : begin adc_cs <= 0; adc_clk <= 1; adc_data[3] <= adc_dat; end //7
8'd19 : begin adc_cs <= 0; adc_clk <= 1; adc_data[2] <= adc_dat; end //8
8'd21 : begin adc_cs <= 0; adc_clk <= 1; adc_data[1] <= adc_dat; end //9
8'd23 : begin adc_cs <= 0; adc_clk <= 1; adc_data[0] <= adc_dat; end //10
default : begin adc_cs <= 1; adc_clk <= 1; end
endcase
endmodule

由于采集到的数据是二进制的电压信号，因此第三部分的代码目的是将采集到的二进制数据转化为BCD码，方便显示与输出。

module bin_BCD
(
input CLKIOS_c ,
input rst_n ,
input [7:0] adc_data ,
output reg [19:0] bcd_code
);

wire [15:0] bin_code = adc_data * 16'd129;
reg [35:0] shift_reg;

always@(bin_code or rst_n)
begin
shift_reg = {20'b0,bin_code};
if(!rst_n) bcd_code = 0;
else
begin
repeat(16)
begin
if (shift_reg[19:16] >= 5) shift_reg[19:16] = shift_reg[19:16] + 2'b11;
if (shift_reg[23:20] >= 5) shift_reg[23:20] = shift_reg[23:20] + 2'b11;
if (shift_reg[27:24] >= 5) shift_reg[27:24] = shift_reg[27:24] + 2'b11;
if (shift_reg[31:28] >= 5) shift_reg[31:28] = shift_reg[31:28] + 2'b11;
if (shift_reg[35:32] >= 5) shift_reg[35:32] = shift_reg[35:32] + 2'b11;
shift_reg = shift_reg << 1;
end
bcd_code = shift_reg[35:16];
end
end
endmodule

第四部分则是将转化为的BCD码显示到OLED屏幕上，也就是显示出电压值。由于在电子森林上有相关的案例和类似的代码，因此此处代码经过改编后可以得到运用。

module OLED
(
input CLKIOS_c, //12MHz系统时钟
input rst_n, //系统复位，低有效

input [19:0] bcd_code, //

output reg oled_csn, //OLCD液晶屏使能
output reg oled_rst, //OLCD液晶屏复位
output reg oled_dcn, //OLCD数据指令控制
output reg oled_clk, //OLCD时钟信号
output reg oled_dat //OLCD数据信号
);

localparam INIT_DEPTH = 16'd25; //LCD初始化的命令的数量
localparam IDLE = 6'h1, MAIN = 6'h2, INIT = 6'h4, SCAN = 6'h8, WRITE = 6'h10, DELAY = 6'h20;
localparam HIGH = 1'b1, LOW = 1'b0;
localparam DATA = 1'b1, CMD = 1'b0;

reg [7:0] cmd [24:0];
reg [39:0] mem [122:0];
reg [7:0] y_p, x_ph, x_pl;
reg [(8*21-1):0] char;
reg [7:0] num, char_reg; //
reg [4:0] cnt_main, cnt_init, cnt_scan, cnt_write;
reg [15:0] num_delay, cnt_delay, cnt;
reg [5:0] state, state_back;

always@(posedge CLKIOS_c or negedge rst_n) begin
if(!rst_n) begin
cnt_main <= 1'b0; cnt_init <= 1'b0; cnt_scan <= 1'b0; cnt_write <= 1'b0;
y_p <= 1'b0; x_ph <= 1'b0; x_pl <= 1'b0;
num <= 1'b0; char <= 1'b0; char_reg <= 1'b0;
num_delay <= 16'd5; cnt_delay <= 1'b0; cnt <= 1'b0;
oled_csn <= HIGH; oled_rst <= HIGH; oled_dcn <= CMD; oled_clk <= HIGH; oled_dat <= LOW;
state <= IDLE; state_back <= IDLE;
end else begin
case(state)
IDLE:begin
cnt_main <= 1'b0; cnt_init <= 1'b0; cnt_scan <= 1'b0; cnt_write <= 1'b0;
y_p <= 1'b0; x_ph <= 1'b0; x_pl <= 1'b0;
num <= 1'b0; char <= 1'b0; char_reg <= 1'b0;
num_delay <= 16'd5; cnt_delay <= 1'b0; cnt <= 1'b0;
oled_csn <= HIGH; oled_rst <= HIGH; oled_dcn <= CMD; oled_clk <= HIGH; oled_dat <= LOW;
state <= MAIN; state_back <= MAIN;
end
MAIN:begin
if(cnt_main >= 5'd8) cnt_main <= 5'd5;
else cnt_main <= cnt_main + 1'b1;
case(cnt_main) //MAIN状态
5'd0: begin state <= INIT; end
5'd1: begin y_p <= 8'hb0; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= " FPGA ";state <= SCAN; end
5'd2: begin y_p <= 8'hb1; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= " ";state <= SCAN; end
5'd3: begin y_p <= 8'hb2; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= " VOLTAGE ";state <= SCAN; end
5'd4: begin y_p <= 8'hb3; x_ph <= 8'h10; x_pl <= 8'h00; num <= 5'd16; char <= " . V ";state <= SCAN; end

5'd5: begin y_p <= 8'hb3; x_ph <= 8'h13; x_pl <= 8'h00; num <= 5'd 1; char <= bcd_code[19:16]; state <= SCAN; end
5'd6: begin y_p <= 8'hb3; x_ph <= 8'h14; x_pl <= 8'h00; num <= 5'd 1; char <= bcd_code[15:12]; state <= SCAN; end
5'd7: begin y_p <= 8'hb3; x_ph <= 8'h15; x_pl <= 8'h00; num <= 5'd 1; char <= bcd_code[11:8]; state <= SCAN; end
5'd8: begin y_p <= 8'hb3; x_ph <= 8'h16; x_pl <= 8'h00; num <= 5'd 1; char <= bcd_code[7:4]; state <= SCAN; end

default: state <= IDLE;
endcase
end
INIT:begin //初始化状态
case(cnt_init)
5'd0: begin oled_rst <= LOW; cnt_init <= cnt_init + 1'b1; end //复位有效
5'd1: begin num_delay <= 16'd25000; state <= DELAY; state_back <= INIT; cnt_init <= cnt_init + 1'b1; end //延时大于3us
5'd2: begin oled_rst <= HIGH; cnt_init <= cnt_init + 1'b1; end //复位恢复
5'd3: begin num_delay <= 16'd25000; state <= DELAY; state_back <= INIT; cnt_init <= cnt_init + 1'b1; end //延时大于220us
5'd4: begin
if(cnt>=INIT_DEPTH) begin //当25条指令及数据发出后，配置完成
cnt <= 1'b0;
cnt_init <= cnt_init + 1'b1;
end else begin
cnt <= cnt + 1'b1; num_delay <= 16'd5;
oled_dcn <= CMD; char_reg <= cmd[cnt]; state <= WRITE; state_back <= INIT;
end
end
5'd5: begin cnt_init <= 1'b0; state <= MAIN; end //初始化完成，返回MAIN状态
default: state <= IDLE;
endcase
end
SCAN:begin //刷屏状态，从RAM中读取数据刷屏
if(cnt_scan == 5'd11) begin
if(num) cnt_scan <= 5'd3;
else cnt_scan <= cnt_scan + 1'b1;
end else if(cnt_scan == 5'd12) cnt_scan <= 1'b0;
else cnt_scan <= cnt_scan + 1'b1;
case(cnt_scan)
5'd 0: begin oled_dcn <= CMD; char_reg <= y_p; state <= WRITE; state_back <= SCAN; end //定位列页地址
5'd 1: begin oled_dcn <= CMD; char_reg <= x_pl; state <= WRITE; state_back <= SCAN; end //定位行地址低位
5'd 2: begin oled_dcn <= CMD; char_reg <= x_ph; state <= WRITE; state_back <= SCAN; end //定位行地址高位

5'd 3: begin num <= num - 1'b1;end
5'd 4: begin oled_dcn <= DATA; char_reg <= 8'h00; state <= WRITE; state_back <= SCAN; end //将5*8点阵编程8*8
5'd 5: begin oled_dcn <= DATA; char_reg <= 8'h00; state <= WRITE; state_back <= SCAN; end //将5*8点阵编程8*8
5'd 6: begin oled_dcn <= DATA; char_reg <= 8'h00; state <= WRITE; state_back <= SCAN; end //将5*8点阵编程8*8
5'd 7: begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][39:32]; state <= WRITE; state_back <= SCAN; end
5'd 8: begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][31:24]; state <= WRITE; state_back <= SCAN; end
5'd 9: begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][23:16]; state <= WRITE; state_back <= SCAN; end
5'd10: begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][15: 8]; state <= WRITE; state_back <= SCAN; end
5'd11: begin oled_dcn <= DATA; char_reg <= mem[char[(num*8)+:8]][ 7: 0]; state <= WRITE; state_back <= SCAN; end
5'd12: begin state <= MAIN; end
default: state <= IDLE;
endcase
end
WRITE:begin //WRITE状态，将数据按照SPI时序发送给屏幕
if(cnt_write >= 5'd17) cnt_write <= 1'b0;
else cnt_write <= cnt_write + 1'b1;
case(cnt_write)
5'd 0: begin oled_csn <= LOW; end //9位数据最高位为命令数据控制位
5'd 1: begin oled_clk <= LOW; oled_dat <= char_reg[7]; end //先发高位数据
5'd 2: begin oled_clk <= HIGH; end
5'd 3: begin oled_clk <= LOW; oled_dat <= char_reg[6]; end
5'd 4: begin oled_clk <= HIGH; end
5'd 5: begin oled_clk <= LOW; oled_dat <= char_reg[5]; end
5'd 6: begin oled_clk <= HIGH; end
5'd 7: begin oled_clk <= LOW; oled_dat <= char_reg[4]; end
5'd 8: begin oled_clk <= HIGH; end
5'd 9: begin oled_clk <= LOW; oled_dat <= char_reg[3]; end
5'd10: begin oled_clk <= HIGH; end
5'd11: begin oled_clk <= LOW; oled_dat <= char_reg[2]; end
5'd12: begin oled_clk <= HIGH; end
5'd13: begin oled_clk <= LOW; oled_dat <= char_reg[1]; end
5'd14: begin oled_clk <= HIGH; end
5'd15: begin oled_clk <= LOW; oled_dat <= char_reg[0]; end //后发低位数据
5'd16: begin oled_clk <= HIGH; end
5'd17: begin oled_csn <= HIGH; state <= DELAY; end //
default: state <= IDLE;
endcase
end
DELAY:begin //延时状态
if(cnt_delay >= num_delay) begin
cnt_delay <= 16'd0; state <= state_back;
end else cnt_delay <= cnt_delay + 1'b1;
end
default:state <= IDLE;
endcase
end
end

//OLED配置指令数据
always@(posedge rst_n)
begin
cmd[ 0] = {8'hae};
cmd[ 1] = {8'h00};
cmd[ 2] = {8'h10};
cmd[ 3] = {8'h00};
cmd[ 4] = {8'hb0};
cmd[ 5] = {8'h81};
cmd[ 6] = {8'hff};
cmd[ 7] = {8'ha1};
cmd[ 8] = {8'ha6};
cmd[ 9] = {8'ha8};
cmd[10] = {8'h1f};
cmd[11] = {8'hc8};
cmd[12] = {8'hd3};
cmd[13] = {8'h00};
cmd[14] = {8'hd5};
cmd[15] = {8'h80};
cmd[16] = {8'hd9};
cmd[17] = {8'h1f};
cmd[18] = {8'hda};
cmd[19] = {8'h00};
cmd[20] = {8'hdb};
cmd[21] = {8'h40};
cmd[22] = {8'h8d};
cmd[23] = {8'h14};
cmd[24] = {8'haf};
end

//5*8点阵字库数据
always@(posedge rst_n)
begin
mem[ 0] = {8'h3E, 8'h51, 8'h49, 8'h45, 8'h3E}; // 48 0
mem[ 1] = {8'h00, 8'h42, 8'h7F, 8'h40, 8'h00}; // 49 1
mem[ 2] = {8'h42, 8'h61, 8'h51, 8'h49, 8'h46}; // 50 2
mem[ 3] = {8'h21, 8'h41, 8'h45, 8'h4B, 8'h31}; // 51 3
mem[ 4] = {8'h18, 8'h14, 8'h12, 8'h7F, 8'h10}; // 52 4
mem[ 5] = {8'h27, 8'h45, 8'h45, 8'h45, 8'h39}; // 53 5
mem[ 6] = {8'h3C, 8'h4A, 8'h49, 8'h49, 8'h30}; // 54 6
mem[ 7] = {8'h01, 8'h71, 8'h09, 8'h05, 8'h03}; // 55 7
mem[ 8] = {8'h36, 8'h49, 8'h49, 8'h49, 8'h36}; // 56 8
mem[ 9] = {8'h06, 8'h49, 8'h49, 8'h29, 8'h1E}; // 57 9
mem[ 10] = {8'h7C, 8'h12, 8'h11, 8'h12, 8'h7C}; // 65 A
mem[ 11] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h36}; // 66 B
mem[ 12] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h22}; // 67 C
mem[ 13] = {8'h7F, 8'h41, 8'h41, 8'h22, 8'h1C}; // 68 D
mem[ 14] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h41}; // 69 E
mem[ 15] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h01}; // 70 F

mem[ 32] = {8'h00, 8'h00, 8'h00, 8'h00, 8'h00}; // 32 sp
mem[ 33] = {8'h00, 8'h00, 8'h2f, 8'h00, 8'h00}; // 33 !
mem[ 34] = {8'h00, 8'h07, 8'h00, 8'h07, 8'h00}; // 34
mem[ 35] = {8'h14, 8'h7f, 8'h14, 8'h7f, 8'h14}; // 35 #
mem[ 36] = {8'h24, 8'h2a, 8'h7f, 8'h2a, 8'h12}; // 36 $
mem[ 37] = {8'h62, 8'h64, 8'h08, 8'h13, 8'h23}; // 37 %
mem[ 38] = {8'h36, 8'h49, 8'h55, 8'h22, 8'h50}; // 38 &
mem[ 39] = {8'h00, 8'h05, 8'h03, 8'h00, 8'h00}; // 39 '
mem[ 40] = {8'h00, 8'h1c, 8'h22, 8'h41, 8'h00}; // 40 (
mem[ 41] = {8'h00, 8'h41, 8'h22, 8'h1c, 8'h00}; // 41 )
mem[ 42] = {8'h14, 8'h08, 8'h3E, 8'h08, 8'h14}; // 42 *
mem[ 43] = {8'h08, 8'h08, 8'h3E, 8'h08, 8'h08}; // 43 +
mem[ 44] = {8'h00, 8'h00, 8'hA0, 8'h60, 8'h00}; // 44 ,
mem[ 45] = {8'h08, 8'h08, 8'h08, 8'h08, 8'h08}; // 45 -
mem[ 46] = {8'h00, 8'h60, 8'h60, 8'h00, 8'h00}; // 46 .
mem[ 47] = {8'h20, 8'h10, 8'h08, 8'h04, 8'h02}; // 47 /
mem[ 48] = {8'h3E, 8'h51, 8'h49, 8'h45, 8'h3E}; // 48 0
mem[ 49] = {8'h00, 8'h42, 8'h7F, 8'h40, 8'h00}; // 49 1
mem[ 50] = {8'h42, 8'h61, 8'h51, 8'h49, 8'h46}; // 50 2
mem[ 51] = {8'h21, 8'h41, 8'h45, 8'h4B, 8'h31}; // 51 3
mem[ 52] = {8'h18, 8'h14, 8'h12, 8'h7F, 8'h10}; // 52 4
mem[ 53] = {8'h27, 8'h45, 8'h45, 8'h45, 8'h39}; // 53 5
mem[ 54] = {8'h3C, 8'h4A, 8'h49, 8'h49, 8'h30}; // 54 6
mem[ 55] = {8'h01, 8'h71, 8'h09, 8'h05, 8'h03}; // 55 7
mem[ 56] = {8'h36, 8'h49, 8'h49, 8'h49, 8'h36}; // 56 8
mem[ 57] = {8'h06, 8'h49, 8'h49, 8'h29, 8'h1E}; // 57 9
mem[ 58] = {8'h00, 8'h36, 8'h36, 8'h00, 8'h00}; // 58 :
mem[ 59] = {8'h00, 8'h56, 8'h36, 8'h00, 8'h00}; // 59 ;
mem[ 60] = {8'h08, 8'h14, 8'h22, 8'h41, 8'h00}; // 60 <
mem[ 61] = {8'h14, 8'h14, 8'h14, 8'h14, 8'h14}; // 61 =
mem[ 62] = {8'h00, 8'h41, 8'h22, 8'h14, 8'h08}; // 62 >
mem[ 63] = {8'h02, 8'h01, 8'h51, 8'h09, 8'h06}; // 63 ?
mem[ 64] = {8'h32, 8'h49, 8'h59, 8'h51, 8'h3E}; // 64 @
mem[ 65] = {8'h7C, 8'h12, 8'h11, 8'h12, 8'h7C}; // 65 A
mem[ 66] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h36}; // 66 B
mem[ 67] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h22}; // 67 C
mem[ 68] = {8'h7F, 8'h41, 8'h41, 8'h22, 8'h1C}; // 68 D
mem[ 69] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h41}; // 69 E
mem[ 70] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h01}; // 70 F
mem[ 71] = {8'h3E, 8'h41, 8'h49, 8'h49, 8'h7A}; // 71 G
mem[ 72] = {8'h7F, 8'h08, 8'h08, 8'h08, 8'h7F}; // 72 H
mem[ 73] = {8'h00, 8'h41, 8'h7F, 8'h41, 8'h00}; // 73 I
mem[ 74] = {8'h20, 8'h40, 8'h41, 8'h3F, 8'h01}; // 74 J
mem[ 75] = {8'h7F, 8'h08, 8'h14, 8'h22, 8'h41}; // 75 K
mem[ 76] = {8'h7F, 8'h40, 8'h40, 8'h40, 8'h40}; // 76 L
mem[ 77] = {8'h7F, 8'h02, 8'h0C, 8'h02, 8'h7F}; // 77 M
mem[ 78] = {8'h7F, 8'h04, 8'h08, 8'h10, 8'h7F}; // 78 N
mem[ 79] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h3E}; // 79 O
mem[ 80] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h06}; // 80 P
mem[ 81] = {8'h3E, 8'h41, 8'h51, 8'h21, 8'h5E}; // 81 Q
mem[ 82] = {8'h7F, 8'h09, 8'h19, 8'h29, 8'h46}; // 82 R
mem[ 83] = {8'h46, 8'h49, 8'h49, 8'h49, 8'h31}; // 83 S
mem[ 84] = {8'h01, 8'h01, 8'h7F, 8'h01, 8'h01}; // 84 T
mem[ 85] = {8'h3F, 8'h40, 8'h40, 8'h40, 8'h3F}; // 85 U
mem[ 86] = {8'h1F, 8'h20, 8'h40, 8'h20, 8'h1F}; // 86 V
mem[ 87] = {8'h3F, 8'h40, 8'h38, 8'h40, 8'h3F}; // 87 W
mem[ 88] = {8'h63, 8'h14, 8'h08, 8'h14, 8'h63}; // 88 X
mem[ 89] = {8'h07, 8'h08, 8'h70, 8'h08, 8'h07}; // 89 Y
mem[ 90] = {8'h61, 8'h51, 8'h49, 8'h45, 8'h43}; // 90 Z
mem[ 91] = {8'h00, 8'h7F, 8'h41, 8'h41, 8'h00}; // 91 [
mem[ 92] = {8'h55, 8'h2A, 8'h55, 8'h2A, 8'h55}; // 92 .
mem[ 93] = {8'h00, 8'h41, 8'h41, 8'h7F, 8'h00}; // 93 ]
mem[ 94] = {8'h04, 8'h02, 8'h01, 8'h02, 8'h04}; // 94 ^
mem[ 95] = {8'h40, 8'h40, 8'h40, 8'h40, 8'h40}; // 95 _
mem[ 96] = {8'h00, 8'h01, 8'h02, 8'h04, 8'h00}; // 96 '
mem[ 97] = {8'h20, 8'h54, 8'h54, 8'h54, 8'h78}; // 97 a
mem[ 98] = {8'h7F, 8'h48, 8'h44, 8'h44, 8'h38}; // 98 b
mem[ 99] = {8'h38, 8'h44, 8'h44, 8'h44, 8'h20}; // 99 c
mem[100] = {8'h38, 8'h44, 8'h44, 8'h48, 8'h7F}; // 100 d
mem[101] = {8'h38, 8'h54, 8'h54, 8'h54, 8'h18}; // 101 e
mem[102] = {8'h08, 8'h7E, 8'h09, 8'h01, 8'h02}; // 102 f
mem[103] = {8'h18, 8'hA4, 8'hA4, 8'hA4, 8'h7C}; // 103 g
mem[104] = {8'h7F, 8'h08, 8'h04, 8'h04, 8'h78}; // 104 h
mem[105] = {8'h00, 8'h44, 8'h7D, 8'h40, 8'h00}; // 105 i
mem[106] = {8'h40, 8'h80, 8'h84, 8'h7D, 8'h00}; // 106 j
mem[107] = {8'h7F, 8'h10, 8'h28, 8'h44, 8'h00}; // 107 k
mem[108] = {8'h00, 8'h41, 8'h7F, 8'h40, 8'h00}; // 108 l
mem[109] = {8'h7C, 8'h04, 8'h18, 8'h04, 8'h78}; // 109 m
mem[110] = {8'h7C, 8'h08, 8'h04, 8'h04, 8'h78}; // 110 n
mem[111] = {8'h38, 8'h44, 8'h44, 8'h44, 8'h38}; // 111 o
mem[112] = {8'hFC, 8'h24, 8'h24, 8'h24, 8'h18}; // 112 p
mem[113] = {8'h18, 8'h24, 8'h24, 8'h18, 8'hFC}; // 113 q
mem[114] = {8'h7C, 8'h08, 8'h04, 8'h04, 8'h08}; // 114 r
mem[115] = {8'h48, 8'h54, 8'h54, 8'h54, 8'h20}; // 115 s
mem[116] = {8'h04, 8'h3F, 8'h44, 8'h40, 8'h20}; // 116 t
mem[117] = {8'h3C, 8'h40, 8'h40, 8'h20, 8'h7C}; // 117 u
mem[118] = {8'h1C, 8'h20, 8'h40, 8'h20, 8'h1C}; // 118 v
mem[119] = {8'h3C, 8'h40, 8'h30, 8'h40, 8'h3C}; // 119 w
mem[120] = {8'h44, 8'h28, 8'h10, 8'h28, 8'h44}; // 120 x
mem[121] = {8'h1C, 8'hA0, 8'hA0, 8'hA0, 8'h7C}; // 121 y
mem[122] = {8'h44, 8'h64, 8'h54, 8'h4C, 8'h44}; // 122 z
end

endmodule

最后一部分也就是顶层模块部分，是对上述四个模块的控制的框架，作用是将前四部分进行分层例化和子程序的调用。

module VOLTAGE
(
input clk ,
input rst_n ,
input adc_dat ,
output adc_clk ,
output adc_cs ,
output oled_csn,
output oled_rst,
output oled_dcn,
output oled_clk,
output oled_dat
);
wire CLKIOS_c,CLKOP_c;
wire [19:0] bcd_code;
wire [7:0] adc_data ;

pll pll
(
.CLKI(clk),
.CLKOP(CLKIOP_c),
.CLKOS(CLKIOS_c)
);
wire adc_done;
ADC v1
(
.CLKIOS_c (CLKIOS_c),
.rst_n (rst_n ),
.adc_dat (adc_dat ),
.adc_clk (adc_clk ),
.adc_cs (adc_cs ),
.adc_done (adc_done ),
.adc_data (adc_data )
);

bin_BCD v2(
.CLKIOS_c (CLKIOS_c ),
.rst_n (rst_n ),
.adc_data (adc_data ),
.bcd_code (bcd_code )
);

OLED v3(
.CLKIOS_c (CLKIOS_c ),
.rst_n (rst_n ),
.bcd_code (bcd_code ),
.oled_csn (oled_csn ),
.oled_rst (oled_rst ),
.oled_dcn (oled_dcn ),
.oled_clk (oled_clk ),
.oled_dat (oled_dat )
);
endmodule

项目结果：

项目总结：

通过本次参与电子森林举办的2021暑假一起练-基于小脚丫FPGA的综合技能训练平台项目，我首次接触并学习了有关FPGA以及开发软件Lattice Diamond的知识。而本次暑期的学习也让我对数字电路的书本知识得到了实践，让我掌握了一门新的开发语言。

在完成项目的过程中，我了解了Verilog，FPGA，运用了ADC的采集，BCD码的转换以及OLED的显示通信等。多个子项目的并行执行让我在思考此类问题时思考方式更加多样，思路也会更加清晰。

虽说是首次接触，但电子森林、硬禾学堂上有许多相关的例题和详细的讲解，因此学习时遇到的一些困难都能获得相关的参考和解决方法，在此，非常感谢电子森林、硬禾学堂提供的平台和帮助！