The PMP9444 reference design provides all the power supply rails necessary to power Xilinx's Kintex UltraScale family of FPGAs. It features two UCD90120A's for flexible power up and power down sequencing as well as voltage monitoring, current monitoring, and voltage margining through the PMB
— By Dennis Hudgins, Low Voltage Applications Manages, Tucson Design Center
来自ADI的模拟对话 Modern FPGAs are among the most complex integrated circuits ever created. They employ the most advanced transistor technology and cutting-edge architectural structures to achieve both incredible flexibility and the highest performance. Over time, as technology has advanced, this complexity has dictated certain compromises in the design and implementation of systems using the FPGAs. This is nowhere more apparent than in the power supplies, which must be ever more accurate, more agile, more controllable, smaller, more efficient, and more fault aware with each new FPGA generation. In this article, we look specifically at some of the constraining specifications for the Altera® Arria 10 FPGA, and what they mean for a power supply design. Then we discuss the best power delivery solutions, and lay out the plan to successfully meet all of the specifications and make our FPGA perform at its optimal efficiency, speed, and power level using Analog Devices’ complete set of power system management (PSM) ICs, including the [LTC3887](https://www.analog.com/en/products/ltc3887.html), [LTC2977](https://www.analog.com/en/products/ltc2977.html), and [LTM4677](https://www.analog.com/en/products/ltm4677.html).
来自美信官网 Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signal processing, medical imaging, and high-performance computing. This application note outlines the issues related to powering FPGAs. It also discusses Maxim's solutions for powering Xilinx® FPGAs.
Renesas官网上提供的白皮书文章，PDF格式 Field-programmable gate arrays (FPGAs) have gained much attention and widespread application in the end market. This document outlines the requirements for FPGA power supply and related issues. It will also discuss the latest digital power module from Renesas, which can be used as a power supply solution for FPGA applications, with a detailed introduction to the ISL8274M as an example. 作者： * Xiao Li, Senior Apps Engineer, Industrial Analog & Power Group, Renesas Electronics Corp. * Billy Yang, Principal Apps Engineer, Industrial Analog & Power Group, Renesas Electronics Corp.
来自Intel/Altera的技术文章 An FPGA power tree is a graphical representation of your system’s power management architecture. The power tree illustrates the main supply power flow through a tree of power converters that convert the main supply power to the voltage and current required to drive various loads. Every FPGA design has unique power consumption requirements requiring a unique power tree. This application note outlines the creation of an FPGA power tree optimized for your FPGA design. Your FPGA has several inputs requiring power for the FPGA to operate. These inputs supply power to various resource blocks within the FPGA, including logic, RAM, digital signal processing (DSP), phaselocked loops (PLLs), clocks, I/Os, and transceivers. These resource blocks have static and dynamic power requirements that vary by your selected FPGA and utilization. Your selected FPGA does not have a fixed power requirement; your total power consumption, and your FPGA power tree, depends on your design.
来自于网站Power Electronics News
nfineon delivers an ideal DC-DC power supply solution for Xilinx® All Programmable FPGAs, SoCs and MPSoCs including VersalTM, Kintex®, Virtex® and Zynq®. The complete power supply ensures high performance and system robustness in all aspects of the design.
Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power on, and soft-start requirements, can result in unreliable power up or potential damage to the FPGA.