ZIPCPU及相关的设计资源

Besides building the toolchain, this post offers a fun way to view how the logic moves its way through the ZipCPU as a result of the three separate ZipCPU prefetch modules.

Building and using an example ZipCPU demonstration design: ZBasic

This discussion also includes a demonstration of what it takes to run 4x4x4 Tic-Tac-Toe on the ZBasic architecture.

Debugging your CPU while on the FPGA

Here, we discuss how the ZipCPU can be halted, stepped, and even reset from the debugging bus.

Building a compromise prefetch module – one that isn’t as light on logic as the basic prefetch, but yet offers more performance than the prefetch and cache module.

The ZipCPU’s interrupt controller

Profiling your CPU using Verilator

This will be about how I was able to measure, and optimize, every clock used by my CPU (as implemented on the XuLA2-LX25 when running the Dhrystone benchmark.

Building a better Verilog Multiply for the ZipCPU

How to debug the ZipCPU when running the ZipOS found on the S6SoC

o How a really simple Operating System works.

Why does blinky make a CPU appear to be so slow?

The ZipCPU meet blinky discussing how to run blinky across multiple threads

Wishbone总线

AXI总线

互联

SoC + FPGA架构

How to interact with an FPGA from a CPU

CPU设计话题

An overview of the ZipCPU instruction set

How to build a back-end for GCC and/or binutils

Debugging a CPU

Putting the pieces together to build a data recorder

How to build a back-end for your soft-core using GDB

DSP话题

Quantization error analysis

Representing angles within an FPGA

Debugging DSP algorithms

A basic histogram implementation, and then what happened when I went to use it

Interpolation

o Nearest Neighbour

o Series: How to build a Linear Interpolator

o Interpolation is just convolution

o Quadratic interpolator

o A filter based upsampling interpolation method

o Polynomial Interpolation a.la Harris

o Why splines are entirely inappropriate for real-time DSP

CIC Filters

o CIC upsampler

o CIC downsampler

Sine, Cosine, and Arctangent calculation

o Table based sin/cos generation

o Quarter wave table based sin/cos generation

o What is a CORDIC, and how do I use it?

Generating Sin/Cos using a CORDIC

Using a CORDIC as a phase measuring device

The basic CORDIC test-bench

Basic logic design of a numerically controlled oscillator

Downconverting an incoming signal using a CORDIC

Generating AM, FM, and QAM types of signals using the CORDIC

o A quadratic table based sin/cos generator, optimized for reduced phase noise and reduced spur energy. This requires two multiplies, and so it improves performance over the CORDIC approach

关于数字滤波器的一些通用话题

o High speed filtering. These filters will run at your system clock speed, or not at all.

A pair of very simple digital filters

The Moving average filter

High speed FIR implementation

An improved high-speed implementation

High speed symmetric FIR implementation

Halfband FIR implementation

Hilbert Transform

o Low-speed filtering. These filters run N times slower than your system clock speed. They are more efficient, if you can use them.

In general, these will be the same filters as their high speed counterparts.

A Generic (slow) FIR filter.

A cascaded slow FIR filter. This article will present an approach that allows you to cascade filter blocks together in order to implement a longer filter.

A symmetric slow FIR filter. This article modifies the generic (slow) FIR filter, in order to optimize it to exploit the linear phase relationship within it. This article goes through the background of why a symmetric filter is, as well as why such an implementation is superior to the generic one.

o Building a delay

o Estimating a filter’s cost

多数率信号处理

o Implementing a downsampler and filter

How to test a digital filter

o Improved PWM: How to generating a cheap audio signal from an I/O pin

o Testing the improved PWM signal

o Building a generic filtering test harness

Evaluating the filter’s frequency response

Testing a generic filter using the test harness

o Finding IIR limit cycles