ProjectF上与FPGA相关的参考资源

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ProjectF上与FPGA相关的参考资源

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ProjectF上与FPGA相关的参考资源

创办者：Will Green

推荐的网站

学习资源

Bruno Levy’s Learn FPGA

论坛

1BitSquared Discord

Digilent Forums

博客

benjamin.computer

Black Mesa Labs

Electronics etc…

Fabien Sanglard

Tales from Beyond the Register Map

Youtube频道

After Hours Engineering

Piotr Esden-Tempski

Zero To ASIC Course

Verilog资源库

图形图像

draw_circle - Draw circle outline

draw_circle_fill - Draw filled circle

draw_line - Bresenham's line algorithm

draw_line_1d.sv - Draw straight line (left to right only)

draw_rectangle - Draw rectangle outline

draw_rectangle_fill - Draw filled rectangle

draw_triangle - Draw triangle outline

draw_triangle_fill - Draw filled triangle

ProjectF在Github上的显示控制器

数学计算

除法

div.sv - fixed point

div_int.sv - integer

线性反馈移位寄存器: lfsr.sv

平方根

sqrt.sv - fixed point

sqrt_int.sv - integer

Trigonometry

sine_table.sv - sine and cosine from ROM

存储

FPGA的存储器类型

用Verilog初始化存储器

ICE40 FPGA中的SPRAM

存储器相关的模块

rom_async.sv - asynchronous ROM in logic (no clock)

rom_sync.sv - synchronous ROM in logic (uses clock)

ice40/bram_sdp.sv - iCE40 simple dual-port block RAM (one read port, one write port)

ice40/spram.sv - iCE40 single port RAM (16-bit data width)

ice40/spram_nibble.sv - iCE40 single port RAM (4-bit data width)

xc7/bram_sdp.sv - XC7 simple dual-port block RAM (one read port, one write port)

UART

uart_baud.sv - UART baud rate generator

uart_rx.sv - UART receiver (to FPGA)

uart_tx.sv - UART transmitter (from FPGA)

正弦查找表

FPGA图形

FPGA图形介绍

Driving a 32×32 RGB LED Matrix by Glen Akins

icestation-32: open-source FPGA game console by Dan Rodrigues

VGA Clock by Matt Venn

Racing the Beam Ray Tracer by Tom Verbeure

FPGA Media Player by ultraembedded

视频格式：VGA、SVGA、720P和1080P

用最少的逻辑实现最快、最色彩丰富的图形

屏幕上的生活

连线和三角形

显示相关的Verilog代码

显示信号产生

display_480p.sv - 640x480 60Hz using traditional VGA timings

display_720p.sv - 1280x720 60Hz (720p)

display_1080p.sv - 1920x1080 60Hz (1080p)

FrameBuffer

framebuffer_bram.sv - framebuffer backed by block RAM (works with XC7 and iCE40)

framebuffer_db_bram.sv - double-buffered framebuffer backed by block RAM (recommended for XC7)

ice40/framebuffer_spram.sv - framebuffer backed by SPRAM (works with iCE40)

ice40/framebuffer_db_spram.sv - double-buffered framebuffer backed by SPRAM (coming soon)

linebuffer.sv - line buffer used by the framebuffer designs for performance and clock isolation

信号编码

tmds_encoder_dvi.sv - TMDS encoder for DVI (HDMI compatible, but no audio)

xc7/dvi_generator.sv - generates a DVI signal on Xilinx 7 Series

xc7/oserdes_10b.sv - 10:1 Output Serializer for Xilinx 7 Series with OSERDESE2

xc7/tmds_out.sv - output TMDS to I/O pins on Xilinx 7 Series with OBUFDS

用FPGA实现数学和算法

Verilog中的数值

Verilog中的定点数

用FPGA的DSP进行乘法计算

用Verilog实现除法

用Verilog实现平方根

工具和测试

用Verilator和SDL进行Verilog仿真

Pong Simulation

Verilating User Guide

Verilog Lint with Verilator

Lazy Foo' Productions

FPGA 1943: The Battle of Midway

Silice Simulation Framework

CXXRTL, a Yosys Simulation Backend

在Linux上构建ICE40 FPGA工具链

在Ubuntu20.04的FPGA工具

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ilovefpga

2021-11-28

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FPGA

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