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A general-purpose drawing program and also a specific-purpose CAD program for circuit schematic drawing and schematic capture.


* Is a schematic capture and simulator. * It is a an IDE for microcontrollers and electronics. * It supports circuit simulation, program development for microcontrollers and simulating the programmed microcontroller together with its application circuit. * Mixed signal


A general purpose circuit simulator with its engine designed to do true mixed-mode simulation. The primary component is a general purpose circuit simulator. It performs nonlinear dc and transient analyses, fourier analysis, and ac analysis. Spice compatible models for the MOSFET (level 1-7), BJT, and diode are included in this release.


Is a switch-level simulator originally originating from Stanford

完整的EDA设计工具 - 电路设计、原理图输入、模拟数字仿真、原型及生产

Is free software for designing printed circuit board layouts. It has many features and is capable of professional-quality output.


Is a free, open-source PCB editor for Microsoft Windows, released under the GNU General Public License. It was designed to be easy to learn and easy to use, yet capable of professional-quality work.


Integrated tool for breadboard, schematic, and PCB design. Targeted at non-engineers (designers, artists, researchers, hobbyists) and users of micro-controller platforms such as Arduino.


KiCad provides for all design stages through the same interface: Schematic capture, PCB layout, Gerber generation/visualization, and library editing are all standard features. It also has a "3D view" feature for PCBs. It is available for all three major operating systems


Is a discrete event simulation environment. Its primary application area is the simulation of communication networks, but because of its generic and flexible architecture, is successfully used in other areas like the simulation of complex IT systems, queueing networks or hardware architectures as well.

混合信号仿真、Verilog + VHDL

Qucs is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter and harmonic balance analysis. Pure digital simulations are also supported using VHDL and/or Verilog.


Is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the "vvp'' command. For synthesis, the compiler generates netlists in the desired format.


Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.


Is a tool to generate metal layers and vias to physically connect together a netlist in a VLSI fabrication technology. It is a maze router, otherwise known as an "over-the-cell" router or "sea-of-gates" router.

VHDL和Verilog RTL编译和综合

Is a chip development program for organizing VHDL and Verilog designs. ChipVault displays designs hierarchically and provides for rapid design navigation and editor launching. ChipVault provides hooks for performing bottom-up tasks such as launching RTL compilers, synthesis, block generation and instantiation, and includes simple to use Revision Control and Issue Tracking systems to help facilitate large group design projects with multiple designers and hundreds of design files.


Is a waveform viewer that can view VCD files produced by most Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools.


Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including custom IC layout (ASICs), schematic drawing, hardware description language specifications, and electro-mechanical hybrid layout


Is a Python package for using Python as a hardware description language.


Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

Verilog RTL综合的框架

Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Selected features and typical applications: * Process almost any synthesizable Verilog-2005 design * Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc. * Built-in formal methods for checking properties and equivalence * Mapping to ASIC standard cell libraries (in Liberty File Format) * Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs * Foundation and/or front-end for custom flows Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base. Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license).


# Arachne-pnr **Arachne-pnr is not maintained anymore; use [nextpnr](https://github.com/YosysHQ/nextpnr) instead, which is a complete functional replacement with major improvements.** ## Updates 2015-08-06: Interface change: Default seed is 1, can be randomized with `-r` option. 2015-07-18: New version. Release notes: * IceStorm and arachne-pnr now support the iCE40LP/HX8K * huge speed improvements (~50x) * arachne-pnr now prints the random seed on each run. The seed can be set with the `-s` option. With the same seed, arachne-pnr should be deterministic across platforms and C++ compilers. ## What is arachne-pnr? Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the [Yosys](http://www.clifford.at/yosys/) [0] synthesis suite for example. It currently targets the Lattice Semiconductor [iCE40](http://www.latticesemi.com/iCE40) family of FPGAs [1]. Its output is a textual bitstream representation for assembly by the [IceStorm](http://www.clifford.at/icestorm/) [2] `icepack` command. The output of `icepack` is a binary bitstream which can be uploaded to a hardware device. Together, Yosys, arachne-pnr and IceStorm provide an fully open-source Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development. ## Warning! This is experimental software! It might have bugs that cause it to produce bitstreams which could damage your FPGA! So when you buy an evaluation board, get a few. We have done extensive verification-based testing (see `tests/`), but so far limited hardware-based testing. This will change. ## Status Arachne-pnr uses a simulated annealing-based algorithm for placement and a multi-pass congestion-based router. Arachne-pnr supports all features documented by IceStorm, although the Block RAM has not been extensively tested. This should include everything on the chip except PLLs and timing information. Support for PLLs is in the works. We hope to support timing information as soon as it is documented by the IceStorm project. ## Installing Arachne-pnr is written in C++11. It has been tested under OSX and Linux with LLVM/Clang and GCC. It should work on Windows, perhaps with a little work. (Patches welcome.) It depends on IceStorm. You should also install Yosys to synthesize designs. To install, just go to the arachne-pnr directory and run ``` $ make && sudo make install ``` ## Invoking/Example Lattice has several low-cost breakout boards: [iCEstick](http://latticesemi.com/iCEstick) for the 1K [3] and [iCE40-HX8K Breakout Board](http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx) [4] for the 8K. There is a simple example for the iCEstick evaluation board in `example/rot` which generates a rotating pattern on the user LEDs. The Verilog input is in `rot.v` and the physical (pin) constraints are in `rot.pcf`. To build it, just run `make`, which executes the following commands: ``` yosys -q -p "synth_ice40 -blif rot.blif" rot.v ../../bin/arachne-pnr -p rot.pcf rot.blif -o rot.txt icepack rot.txt rot.bin ``` You can use the Lattice tools or `iceprog` from IceStorm to upload `rot.bin` onto the board. ## Feedback Feedback, feature requests, bug reports and patches welcome. Please email the author, Cotton Seed , or submit a issue on Github. ## Acknowledgements Arachne-pnr would not have been possible without Clifford Wolf and Mathias Lasser's IceStorm project to reverse-engineer the iCE40 FPGAs and build supporting tools. Also, it would not be useful without Clifford Wolf's Yosys project to synthesize and technology map designs. Thanks to contributors Larry Doolittle, jhol, laanwj, Clifford Wolf (cliffordwolf) and zeldin. ## References [0] http://www.clifford.at/yosys/ [1] http://www.latticesemi.com/iCE40 [2] http://www.clifford.at/icestorm/ [3] http://latticesemi.com/iCEstick [4] http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx


nextpnr -- a portable FPGA place and route tool =============================================== nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. Currently nextpnr supports: * Lattice iCE40 devices supported by [Project IceStorm](http://www.clifford.at/icestorm/) * *(experimental)* Lattice ECP5 devices supported by [Project Trellis](https://github.com/SymbiFlow/prjtrellis) * *(experimental)* a "generic" back-end for user-defined architectures We hope to see Xilinx 7 Series thanks to [Project X-Ray](https://github.com/SymbiFlow/prjxray) and even more FPGA families supported in the future. We would love your help in developing this awesome new project! A brief (academic) paper describing the Yosys+nextpnr flow can be found on [arXiv](https://arxiv.org/abs/1903.10407). Here is a screenshot of nextpnr for iCE40. Build instructions and [getting started notes](#getting-started) can be found below. See also: - [F.A.Q.](docs/faq.md) - [Architecture API](docs/archapi.md) Prerequisites ------------- The following packages need to be installed for building nextpnr, independent of the selected architecture: - CMake 3.3 or later - Modern C++11 compiler (`clang-format` required for development) - Qt5 or later (`qt5-default` for Ubuntu 16.04) - Python 3.5 or later, including development libraries (`python3-dev` for Ubuntu) - on Windows make sure to install same version as supported by [vcpkg](https://github.com/Microsoft/vcpkg/blob/master/ports/python3/CONTROL) - Boost libraries (`libboost-dev libboost-filesystem-dev libboost-thread-dev libboost-program-options-dev libboost-python-dev libboost-dev` or `libboost-all-dev` for Ubuntu) - Eigen3 (`libeigen3-dev` for Ubuntu) is required to build the analytic placer - Latest git Yosys is required to synthesise the demo design - For building on Windows with MSVC, usage of vcpkg is advised for dependency installation. - For 32 bit builds: `vcpkg install boost-filesystem boost-program-options boost-thread boost-python qt5-base eigen3` - For 64 bit builds: `vcpkg install boost-filesystem:x64-windows boost-program-options:x64-windows boost-thread:x64-windows boost-python:x64-windows qt5-base:x64-windows eigen3:x64-windows` - For static builds, add `-static` to each of the package names. For example, change `eigen3:x64-windows` to `eigen3:x64-windows-static` - A copy of Python that matches the version in vcpkg (currently Python 3.6.4). You can download the [Embeddable Zip File](https://www.python.org/downloads/release/python-364/) and extract it. You may need to extract `python36.zip` within the embeddable zip file to a new directory called "Lib". - For building on macOS, brew utility is needed. - Install all needed packages `brew install cmake python boost boost-python3 qt5 eigen` - Do not forget to add qt5 in path as well `echo 'export PATH="/usr/local/opt/qt/bin:$PATH"' >> ~/.bash_profile` Getting started --------------- ### nextpnr-ice40 To build the iCE40 version of nextpnr, install [icestorm](http://www.clifford.at/icestorm/) with chipdbs installed in `/usr/local/share/icebox`, or another location, which should be passed as `-DICEBOX_ROOT=/path/to/share/icebox` (ensure to point it to `share/icebox` and not where the icebox binaries are installed) to CMake. Then build and install `nextpnr-ice40` using the following commands: ``` cmake -DARCH=ice40 . make -j$(nproc) sudo make install ``` On Windows, you may specify paths explicitly: ``` cmake -DARCH=ice40 -DICEBOX_ROOT=C:/ProgramData/icestorm/share/icebox -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake -DVCPKG_TARGET_TRIPLET=x64-windows -G "Visual Studio 15 2017 Win64" -DPYTHON_EXECUTABLE=C:/Python364/python.exe -DPYTHON_LIBRARY=C:/vcpkg/packages/python3_x64-windows/lib/python36.lib -DPYTHON_INCLUDE_DIR=C:/vcpkg/packages/python3_x64-windows/include/python3.6 cmake --build . --config Release ``` To build a static release, change the target triplet from `x64-windows` to `x64-windows-static` and add `-DBUILD_STATIC=ON`. A simple example that runs on the iCEstick dev board can be found in `ice40/examples/blinky/blinky.*`. Usage example: ``` cd ice40/examples/blinky yosys -p 'synth_ice40 -top blinky -json blinky.json' blinky.v # synthesize into blinky.json nextpnr-ice40 --hx1k --json blinky.json --pcf blinky.pcf --asc blinky.asc # run place and route icepack blinky.asc blinky.bin # generate binary bitstream file iceprog blinky.bin # upload design to iCEstick ``` Running nextpnr in GUI mode: ``` nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc --gui ``` (Use the toolbar buttons or the Python command console to perform actions such as pack, place, route, and write output files.) ### nextpnr-ecp5 For ECP5 support, you must download [Project Trellis](https://github.com/SymbiFlow/prjtrellis), then follow its instructions to download the latest database and build _libtrellis_. ``` cmake -DARCH=ecp5 -DTRELLIS_ROOT=/path/to/prjtrellis . make -j$(nproc) sudo make install ``` - For an ECP5 blinky on the 45k ULX3S board, first synthesise using `yosys blinky.ys` in `ecp5/synth`. - Then run ECP5 place-and route using `./nextpnr-ecp5 --json ecp5/synth/blinky.json --basecfg ecp5/synth/ulx3s_empty.config --textcfg ecp5/synth/ulx3s_out.config` - Create a bitstream using `ecppack ulx3s_out.config ulx3s.bit` - Note that `ulx3s_empty.config` contains fixed/unknown bits to be copied to the output bitstream - More examples of the ECP5 flow for a range of boards can be found in the [Project Trellis Examples](https://github.com/SymbiFlow/prjtrellis/tree/master/examples). ### nextpnr-generic The generic target allows running placement and routing for arbitrary custom architectures. ``` cmake -DARCH=generic . make -j$(nproc) sudo make install ``` TBD: Getting started example for generic target. Additional notes for building nextpnr ------------------------------------- Use cmake `-D` options to specify which version of nextpnr you want to build. Use `-DARCH=...` to set the architecture. It is a semicolon separated list. Use `cmake . -DARCH=all` to build all supported architectures. The following runs a debug build of the iCE40 architecture without GUI, without Python support, without the HeAP analytic placer and only HX1K support: ``` cmake -DARCH=ice40 -DCMAKE_BUILD_TYPE=Debug -DBUILD_PYTHON=OFF -DBUILD_GUI=OFF -DBUILD_HEAP=OFF -DICE40_HX1K_ONLY=1 . make -j$(nproc) ``` To make static build relase for iCE40 architecture use the following: ``` cmake -DARCH=ice40 -DBUILD_PYTHON=OFF -DBUILD_GUI=OFF -DSTATIC_BUILD=ON . make -j$(nproc) ``` The HeAP placer's solver can optionally use OpenMP for a speedup on very large designs. Enable this by passing `-DUSE_OPENMP=yes` to cmake (compiler support may vary). You can change the location where nextpnr will be installed (this will usually default to `/usr/local`) by using `-DCMAKE_INSTALL_PREFIX=/install/prefix`. Notes for developers -------------------- - All code is formatted using `clang-format` according to the style rules in `.clang-format` (LLVM based with increased indent widths and brace wraps after classes). - To automatically format all source code, run `make clangformat`. - See the wiki for additional documentation on the architecture API. Testing ------- - To build test binaries as well, use `-DBUILD_TESTS=ON` and after `make` run `make tests` to run them, or you can run separate binaries. - To use code sanitizers use the `cmake` options: - `-DSANITIZE_ADDRESS=ON` - `-DSANITIZE_MEMORY=ON -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++` - `-DSANITIZE_THREAD=ON` - `-DSANITIZE_UNDEFINED=ON` - Running valgrind example `valgrind --leak-check=yes --tool=memcheck ./nextpnr-ice40 --json ice40/blinky.json` - Running tests with code coverage use `-DBUILD_TESTS=ON -DCOVERAGE` and after `make` run `make ice40-coverage` - After that open `ice40-coverage/index.html` in your browser to view the coverage report - Note that `lcov` is needed in order to generate reports Links and references -------------------- ### Synthesis, simulation, and logic optimization - [Yosys](http://www.clifford.at/yosys/) - [Icarus Verilog](http://iverilog.icarus.com/) - [ABC](https://people.eecs.berkeley.edu/~alanmi/abc/) ### FPGA bitstream documentation (and tools) projects - [Project IceStorm (Lattice iCE40)](http://www.clifford.at/icestorm/) - [Project Trellis (Lattice ECP5)](https://symbiflow.github.io/prjtrellis-db/) - [Project X-Ray (Xilinx 7-Series)](https://symbiflow.github.io/prjxray-db/) - [Project Chibi (Intel MAX-V)](https://github.com/rqou/project-chibi) ### Other FOSS FPGA place and route projects - [Arachne PNR](https://github.com/cseed/arachne-pnr) - [VPR/VTR](https://verilogtorouting.org/) - [SymbiFlow](https://github.com/SymbiFlow/symbiflow-arch-defs) - [Gaffe](https://github.com/gaffe-logic/gaffe) - [KinglerPAR](https://github.com/rqou/KinglerPAR)

针对iCE40 FPGA的分析和创建位流的工具

Project IceStorm aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. The IceStorm flow (Yosys, Arachne-pnr, and IceStorm) is a fully open source Verilog-to-Bitstream flow for iCE40 FPGAs. The focus of the project is on the iCE40 LP/HX 1K/4K/8K chips. (Most of the work was done on HX1K-TQ144 and HX8K-CT256 parts.) The iCE40 UltraPlus parts are also supported, including DSPs, oscillators, RGB and SPRAM. iCE40 LM, Ultra and UltraLite parts are not yet supported.


### Migen (Milkymist generator) #### A Python toolbox for building complex digital hardware Despite being faster than schematics entry, hardware design with Verilog and VHDL remains tedious and inefficient for several reasons. The event-driven model introduces issues and manual coding that are unnecessary for synchronous circuits, which represent the lion's share of today's logic designs. Counter- intuitive arithmetic rules result in steeper learning curves and provide a fertile ground for subtle bugs in designs. Finally, support for procedural generation of logic (metaprogramming) through "generate" statements is very limited and restricts the ways code can be made generic, reused and organized. To address those issues, we have developed the **Migen FHDL** library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design's logic to be constructed by a Python program. This last point enables hardware designers to take advantage of the richness of the Python language - object oriented programming, function parameters, generators, operator overloading, libraries, etc. - to build well organized, reusable and elegant designs. Other Migen libraries are built on FHDL and provide various tools such as a system-on-chip interconnect infrastructure, a dataflow programming system, a more traditional high-level synthesizer that compiles Python routines into state machines with datapaths, and a simulator that allows test benches to be written in Python. See the doc/ folder for more technical information. Migen is designed for Python 3.5. Note that Migen is **not** spelled MiGen. #### Quick Links Code repository: https://github.com/m-labs/migen System-on-chip design based on Migen: https://github.com/m-labs/misoc Online documentation: https://m-labs.hk/migen/manual/ #### Quick intro ```python from migen import * from migen.build.platforms import m1 plat = m1.Platform() led = plat.request("user_led") m = Module() counter = Signal(26) m.comb += led.eq(counter[25]) m.sync += counter.eq(counter + 1) plat.build(m) ``` #### License Migen is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use Migen for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible: * tell us that you are using Migen * put the Migen logo (doc/migen_logo.svg) on the page of a product using it, with a link to http://m-labs.hk * cite Migen in publications related to research it has helped * send us feedback and suggestions for improvements * send us bug reports when something goes wrong * send us the modifications and improvements you have done to Migen. The use of "git format-patch" is recommended. If your submission is large and complex and/or you are not sure how to proceed, feel free to discuss it on the mailing list or IRC (#m-labs on Freenode) beforehand. See LICENSE file for full copyright and license info. You can contact us on the public mailing list devel [AT] lists.m-labs.hk. "Electricity! It's like magic!"


Is a waveform viewer for the output of analog electronic circuit simulators such as spice. It displays the data as 2-D plots, andallows for interactive scrolling, zooming, and measuring of thewaveforms


Is a free software data analysis and visualization application built on the KDE Platform


Is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler.


Magic is a venerable VLSI layout tool. Magic VLSI remains popular with universities and small companies. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

IC Layout编辑器

Is a cross-platform IC layout editor supporting GDS, OASIS and CIF formats. It is an open source project licensed under the GNU General Public License. The project is under active development. focuses on rendering speed and quality of the screen output.


A tool for comparing netlists, in analog or mixed-signal circuits that cannot be simulated in reasonable time.


Dragon is a fast, effective standard-cell placement tool for both variable-die and fixed-die ASIC design. It was designed and implemented by NuCAD group in Dept. of ECE, Northwestern University, and ERLAB in Computer Science Dept., UCLA. Dragon does wirelength and routability optimization by combining powerful hypergraph partitioning package (hMetis) with simulated annealing technique. It is a university tool that produces high-quality placement comparable with commercial software such as ITools (formerly TimberWolf) and Cadence QPlace.


FGR is free open-source software for global routing, based on Lagrange Multipliers --- an approach similar to what industry routers use, but with greater mathematical rigor and robust performance. Unlike most other academic tools, FGR is self-contained and does not rely on ILP or external Steiner-tree constructors.


Is a tool to generate metal layers and vias to physically connect together a netlist in a VLSI fabrication technology. It is a maze router, otherwise known as an "over-the-cell" router or "sea-of-gates" router.


Open Source - VHDL Verification Methodology (OS-VVM) delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.


Helps you perform verification by providing a set of capabilities that access HDL signals and enable actions based on changes in the values of these signals.

基于Java API的数字电路验证工具

Is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language.


Clunky class library for digital design.